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    • 3. 发明授权
    • Variable work function transistor high density mask ROM
    • 可变功函数晶体管高密度掩膜ROM
    • US06417548B1
    • 2002-07-09
    • US09356679
    • 1999-07-19
    • Shing-Ren SheuCheng-Chih Kung
    • Shing-Ren SheuCheng-Chih Kung
    • H01L2976
    • H01L27/11233H01L27/1052H01L27/112
    • A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.
    • 掩模ROM通过选择FET阵列中每个FET的栅极的功函数来存储信息。 一些FET的多晶硅栅极被掺杂为N型,并且其它FET的栅极被掺杂P型以形成具有不同功函数的栅极,从而形成具有不同阈值电压的FET。 该ROM由在衬底中形成的掩埋N +位线的平行阵列,沉积在位线上的栅极氧化物层和沉积在栅极氧化物上的多晶硅层组成。 多晶硅是覆盖掺杂P型,然后形成编码掩模,其中编码掩模中的开口暴露多晶硅的区域,以形成具有低阈值电压的FET的栅极。 砷或磷通过掩模开口掺杂到多晶硅中。 去除掩模,沉积诸如硅化钨的导电材料层,并且将多晶硅和导电材料形成为ROM的字线。 ROM的字线用作FET的栅极,位线用作FET的源极和漏极。
    • 4. 发明授权
    • Short turn around time mask ROM process
    • 短周转时间掩码ROM进程
    • US6054353A
    • 2000-04-25
    • US746855
    • 1996-11-18
    • Shing-Ren SheuCheng-Chih Kung
    • Shing-Ren SheuCheng-Chih Kung
    • H01L21/8246H01L21/8234
    • H01L27/11293H01L27/1126
    • A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer. The implantation converts individual gate electrodes from N-type to P-type to alter the threshold voltage of the selected transistors. Relatively few additional processing steps are needed after the programming to complete the ROM.
    • 掩模ROM通过在ROM的制造中的晚期阶段选择FET的阵列中的每个FET的栅极的功函数来存储信息。 一些FET的多晶硅栅极被掺杂为N型,并且其它FET的栅极被掺杂P型以形成具有不同功函数的栅极,从而形成具有不同阈值电压的FET。 该ROM由在衬底中形成的掩埋N +位线的平行阵列,沉积在位线上的栅极氧化物层和沉积在栅极氧化物上的多晶硅层组成。 多晶硅是覆盖N掺杂的,栅极通过光刻法定义,然后在栅电极上形成自对准的硅化物层。 然后在栅电极上形成绝缘层。 ROM的编程通过在绝缘层上形成掩模然后通过掩模中的开口通过绝缘层和硅化物层注入离子并进入多晶硅层来实现。 注入将单个栅电极从N型转换为P型,以改变所选晶体管的阈值电压。 在编程完成ROM之后,需要较少的附加处理步骤。