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1. 发明授权

US07304367B2 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs 有权
标题翻译：金属绝缘体金属电容器，包括掺杂多晶硅接触插头上的过渡金属硅化物膜
公开(公告)号：US07304367B2
公开(公告)日：2007-12-04
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

2. 发明申请

US20050023640A1 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs and methods of forming the same 有权
标题翻译：包括掺杂多晶硅接触插塞上的过渡金属硅化物膜的金属 - 绝缘体 - 金属电容器及其形成方法
公开(公告)号：US20050023640A1
公开(公告)日：2005-02-03
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L27/108 , H01L21/02 , G02F1/136 , H01L21/20 , H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

3. 发明授权

US06995071B2 Methods of forming MIM type capacitor structures using low temperature plasma processing 有权
标题翻译：使用低温等离子体处理形成MIM型电容器结构的方法
公开(公告)号：US06995071B2
公开(公告)日：2006-02-07
申请号：US10830214
申请日：2004-04-22
申请人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
发明人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
IPC分类号： H10L21/8242
CPC分类号： H01L27/10852 , C23C16/405 , C23C16/56 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/02356 , H01L21/31645 , H01L27/10817 , H01L27/10855 , H01L28/91 , Y10S438/957
摘要： Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.
摘要翻译：在集成电路存储器件中形成金属 - 绝缘体 - 金属型电容器的方法可以包括在低温等离子体处理中在电容器结构的下部电极上结晶HfO 2/2电介质层，温度范围为约250摄氏度和约450摄氏度。上电极可以形成在HfO 2 2电介质层上。

4. 发明授权

US07314806B2 Methods of forming metal-insulator-metal (MIM) capacitors with separate seed 有权
标题翻译：用分离的种子形成金属 - 绝缘体 - 金属（MIM）电容器的方法
公开(公告)号：US07314806B2
公开(公告)日：2008-01-01
申请号：US11097404
申请日：2005-04-01
申请人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
发明人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
IPC分类号： H01L21/20
CPC分类号： H01L21/31122
摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
摘要翻译：可以在金属 - 绝缘体 - 金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮化物种子电介质层。金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应电容器。包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

5. 发明申请

US20050227432A1 Methods of forming metal-insulator-metal (MIM) capacitors with separate seed and main dielectric layers and MIM capacitors so formed 有权
标题翻译：形成金属 - 绝缘体 - 金属（MIM）电容器的方法，该电容器具有单独的种子和主电介质层以及如此形成的MIM电容器
公开(公告)号：US20050227432A1
公开(公告)日：2005-10-13
申请号：US11097404
申请日：2005-04-01
申请人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
发明人： Jae-hyoung Choi , Sung-tae Kim , Ki-chul Kim , Cha-young Yoo , Jeong-hee Chung , Se-hoon Oh , Jeong-sik Choi
IPC分类号： H01L27/108 , H01L21/311 , H01L21/8242
CPC分类号： H01L21/31122
摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
摘要翻译：可以在间绝缘子金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮氧化物种子电介质层。金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应电容器。包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

6. 发明授权

US08344439B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same 有权
标题翻译：集成电路电容器，其中包含结晶抑制区域的复合电介质层及其形成方法
公开(公告)号：US08344439B2
公开(公告)日：2013-01-01
申请号：US13171163
申请日：2011-06-28
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

7. 发明申请

US20100187655A1 Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same 有权
标题翻译：具有复合介质层的集成电路电容器，其中包含结晶抑制区域和形成方法
公开(公告)号：US20100187655A1
公开(公告)日：2010-07-29
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

8. 发明授权

US07973352B2 Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
标题翻译：具有包含结晶抑制区域的复合电介质层的电容器
公开(公告)号：US07973352B2
公开(公告)日：2011-07-05
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

9. 发明授权

US07723770B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions 有权
标题翻译：集成电路电容器，其中包含结晶抑制区的复合介电层
公开(公告)号：US07723770B2
公开(公告)日：2010-05-25
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L27/108
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

10. 发明申请

US20060046380A1 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same 有权
公开(公告)号：US20060046380A1
公开(公告)日：2006-03-02
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L21/8244
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

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