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1. 发明申请

US20130034963A1 METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20130034963A1
公开(公告)日：2013-02-07
申请号：US13474764
申请日：2012-05-18
申请人： Byung-hong Chung , Cha-young Yoo , Dong-hyun Kim
发明人： Byung-hong Chung , Cha-young Yoo , Dong-hyun Kim
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0217 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31116 , H01L27/0207 , H01L27/10888 , H01L27/10891 , H01L27/11568
摘要： Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.
摘要翻译：形成用于半导体器件的精细图案的方法包括在蚀刻目标层上形成硬掩模层; 在所述硬掩模层上形成含碳层; 通过蚀刻含碳层形成含碳层图案; 形成覆盖每个含碳层图案的相对侧壁的间隔物; 去除含碳层图案; 通过使用间隔物作为第一蚀刻掩模蚀刻硬掩模层来形成硬掩模图案; 以及通过使用所述硬掩模图案蚀刻所述蚀刻目标层的第二蚀刻掩模。

2. 发明授权

US08889560B2 Methods of forming fine patterns for semiconductor device 有权
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US08889560B2
公开(公告)日：2014-11-18
申请号：US13474764
申请日：2012-05-18
申请人： Byung-hong Chung , Cha-young Yoo , Dong-hyun Kim
发明人： Byung-hong Chung , Cha-young Yoo , Dong-hyun Kim
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/033 , H01L27/108 , H01L21/308 , H01L27/02 , H01L27/115 , H01L21/02
CPC分类号： H01L21/32139 , H01L21/0217 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31116 , H01L27/0207 , H01L27/10888 , H01L27/10891 , H01L27/11568
摘要： Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.
摘要翻译：形成用于半导体器件的精细图案的方法包括在蚀刻目标层上形成硬掩模层; 在所述硬掩模层上形成含碳层; 通过蚀刻含碳层形成含碳层图案; 形成覆盖每个含碳层图案的相对侧壁的间隔物; 去除含碳层图案; 通过使用间隔物作为第一蚀刻掩模蚀刻硬掩模层来形成硬掩模图案; 以及通过使用所述硬掩模图案蚀刻所述蚀刻目标层的第二蚀刻掩模。

3. 发明申请

US20130130465A1 METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS 审中-公开
标题翻译：形成具有包含结晶区域的复合介电层的集成电路电容器的方法
公开(公告)号：US20130130465A1
公开(公告)日：2013-05-23
申请号：US13716901
申请日：2012-12-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoo Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoo Oh
IPC分类号： H01L29/92
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

4. 发明申请

US20120276721A1 METHOD OF FORMING AN OXIDE LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE OXIDE LAYER 有权
标题翻译：形成氧化物层的方法和制造包括氧化物层的半导体器件的方法
公开(公告)号：US20120276721A1
公开(公告)日：2012-11-01
申请号：US13459136
申请日：2012-04-28
申请人： Suk-jin Chung , Jong-cheol Lee , Youn-soo Kim , Cha-young Yoo , Sang-yeol Kang
发明人： Suk-jin Chung , Jong-cheol Lee , Youn-soo Kim , Cha-young Yoo , Sang-yeol Kang
IPC分类号： H01L21/20
CPC分类号： H01L21/02178 , H01L21/02164 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/022 , H01L21/0228 , H01L21/02304 , H01L21/02312 , H01L21/28282 , H01L27/10817 , H01L27/10852 , H01L27/1157 , H01L27/11582 , H01L28/91 , H01L29/66795 , H01L29/7926
摘要： A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.
摘要翻译：一种形成氧化物层的方法。该方法包括：在基板的表面上形成反应抑制性官能团层; 在反应抑制官能团的层上形成金属或半导体的前体层; 以及氧化金属或半导体的前体以获得金属氧化物或半导体氧化物的层。根据该方法，可以形成具有高厚度均匀性的氧化物层，并且可以制造具有优异电特性的半导体器件。

5. 发明申请

US20090124071A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090124071A1
公开(公告)日：2009-05-14
申请号：US12270033
申请日：2008-11-13
申请人： Dong-chul Yoo , Han-mei Choi , Kwang-hee Lee , Kyong-won An , Cha-young Yoo
发明人： Dong-chul Yoo , Han-mei Choi , Kwang-hee Lee , Kyong-won An , Cha-young Yoo
IPC分类号： H01L21/28 , H01L21/316
CPC分类号： H01L29/792 , H01L21/02178 , H01L21/02181 , H01L21/022 , H01L21/02271 , H01L21/02337 , H01L21/3115 , H01L21/3162 , H01L21/31645 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：在其上形成有栅极绝缘层的基板上形成电荷存储层; 使用包括金属氧化物层前体和第一氧化剂的第一反应源在电荷存储层上形成第一金属氧化物层，并且使用包括第二氧化剂的第二反应源将第一金属氧化物层改变为第二金属氧化物层具有比第一氧化剂更大的氧化能力，并且重复形成第一金属氧化物层和将第一金属氧化物层改变为第二金属氧化物层数次以形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成电极层。

6. 发明申请

US20060148193A1 Methods for forming ruthenium films with beta-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same 审中-公开
标题翻译：用含有钌络合物的β-二酮形成钌膜的方法及使用其制造金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US20060148193A1
公开(公告)日：2006-07-06
申请号：US11374349
申请日：2006-03-13
申请人： Kwang-hee Lee , Cha-young Yoo , Han-Jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
发明人： Kwang-hee Lee , Cha-young Yoo , Han-Jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , H01L21/28556 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).
摘要翻译：提供1）一种在单一工艺条件下形成钌膜的方法，由此保持钌膜对下层的高附着性，以及2）使用这种方法制造金属 - 绝缘体 - 金属（MIM）电容器的方法钌膜成型方法。形成钌膜的方法包括以0.2-1ccm的流速和20-60sccm的流量的氧供给双（异庚烷-2,4-二酮）降冰片二烯钌，并将钌膜以在0.5-5乇的压力下使用化学气相沉积（CVD）来制备330-430℃。

7. 发明授权

US07042042B2 Integrated circuit capacitors having a dielectric layer between a U-shaped lower electrode and a support layer 失效
标题翻译：具有在U形下电极和支撑层之间的介电层的集成电路电容器
公开(公告)号：US07042042B2
公开(公告)日：2006-05-09
申请号：US10665093
申请日：2003-09-17
申请人： Seok-jun Won , Cha-young Yoo
发明人： Seok-jun Won , Cha-young Yoo
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Integrated circuit capacitors are provided having an electrically insulating electrode support layer having an opening therein on an integrated circuit substrate. A U-shaped lower electrode is provided in the opening and a first capacitor dielectric layer extends on an inner surface and an outer portion of the U-shaped lower electrode. A second capacitor dielectric layer extends between the outer portion of the U-shaped lower electrode and the first capacitor dielectric and also extends between the outer portion of the U-shaped lower electrode and an inner sidewall of the opening. An upper electrode extends on the first dielectric layer.
摘要翻译：提供集成电路电容器，其具有在集成电路基板上具有开口的电绝缘电极支撑层。 U形下电极设置在开口中，第一电容器电介质层在U形下电极的内表面和外部部分上延伸。第二电容器电介质层在U形下电极的外部部分和第一电容器电介质之间延伸并且还在U形下电极的外部部分和开口的内侧壁之间延伸。上电极在第一电介质层上延伸。

8. 发明申请

US20060046380A1 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same 有权
公开(公告)号：US20060046380A1
公开(公告)日：2006-03-02
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L21/8244
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

9. 发明申请

US20050161727A1 Integrated circuit devices having a metal-insulator-metal (MIM) capacitor 审中-公开
标题翻译：具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件
公开(公告)号：US20050161727A1
公开(公告)日：2005-07-28
申请号：US11083874
申请日：2005-03-18
申请人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
发明人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L28/60 , H01L27/10855 , H01L28/91
摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
摘要翻译：在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。电介质层位于下电极上，电容器的上电极位于电介质层上。在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。接触塞设置在阻挡层上的孔中。电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。电介质层位于下电极上，电容器的上电极位于电介质层上。

10. 发明授权

US06884673B2 Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor 有权
标题翻译：形成具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件的方法
公开(公告)号：US06884673B2
公开(公告)日：2005-04-26
申请号：US10160646
申请日：2002-05-31
申请人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
发明人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/60 , H01L27/10855 , H01L28/91
摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
摘要翻译：在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。电介质层位于下电极上，电容器的上电极位于电介质层上。在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。接触塞设置在阻挡层上的孔中。电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。电介质层位于下电极上，电容器的上电极位于电介质层上。

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