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1. 发明授权

US06532525B1 Method and apparatus for accessing memory 有权
标题翻译：访问存储器的方法和装置
公开(公告)号：US06532525B1
公开(公告)日：2003-03-11
申请号：US09675368
申请日：2000-09-29
申请人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
发明人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G09G5/39 , Y02D10/14
摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.
摘要翻译：公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。响应于存储器桥请求，多个存储器将以第二数据速率访问多个数据。当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

2. 发明授权

US06502173B1 System for accessing memory and method therefore 有权
标题翻译：因此，访问内存和方法的系统
公开(公告)号：US06502173B1
公开(公告)日：2002-12-31
申请号：US09675293
申请日：2000-09-29
申请人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
发明人： Milivoje Aleksic , Grigory Temkine , Oleg Drapkin , Carl Mizuyabu , Adrian Hartog
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G06F13/1605 , Y02D10/14
摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.
摘要翻译：公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。响应于存储器桥请求，多个存储器将访问多个数据第二数据速率。当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。

3. 发明申请

US20050046633A1 Method and apparatus for graphics rendering on a mobile device 有权
标题翻译：用于移动设备上图形呈现的方法和装置
公开(公告)号：US20050046633A1
公开(公告)日：2005-03-03
申请号：US10647772
申请日：2003-08-25
申请人： Milivoje Aleksic , Adrian Hartog
发明人： Milivoje Aleksic , Adrian Hartog
IPC分类号： G06T1/00 , G06T15/00
CPC分类号： G06T15/005 , G09G5/363
摘要： A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.
摘要翻译：用于在移动设备中呈现的图形的方法和装置包括能够接收多个呈现命令的命令队列，generate_event命令和wait_until命令。 wait_until命令对应于由generate_event命令指示的特定操作的完成。该方法和装置还包括可操作地耦合到命令队列的直接存储器访问装置，其中DMA装置能够响应于generate_event命令而接收存储器访问命令。存储器设备能够存储渲染信息，其中响应于generate_event命令可访问存储器设备。此外，该方法和装置包括能够响应于wait_until命令排队渲染命令的命令队列，直到由generate_event命令指示的操作完成为止。

4. 发明授权

US07057620B2 Method and apparatus for graphics rendering on a mobile device 有权
标题翻译：用于移动设备上图形呈现的方法和装置
公开(公告)号：US07057620B2
公开(公告)日：2006-06-06
申请号：US10647772
申请日：2003-08-25
申请人： Milivoje Aleksic , Adrian Hartog
发明人： Milivoje Aleksic , Adrian Hartog
IPC分类号： G06T1/00 , G06F15/00
CPC分类号： G06T15/005 , G09G5/363
摘要： A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.
摘要翻译：用于在移动设备中呈现的图形的方法和装置包括能够接收多个呈现命令的命令队列，generate_event命令和wait_until命令。 wait_until命令对应于由generate_event命令指示的特定操作的完成。该方法和装置还包括可操作地耦合到命令队列的直接存储器访问装置，其中DMA装置能够响应于generate_event命令而接收存储器访问命令。存储器设备能够存储渲染信息，其中响应于generate_event命令可访问存储器设备。此外，该方法和装置包括能够响应于wait_until命令排队渲染命令的命令队列，直到由generate_event命令指示的操作完成为止。

5. 发明授权

US06445394B1 Serialized mapped memory configuration for a video graphics chip 有权
标题翻译：视频图形芯片的序列化映射内存配置
公开(公告)号：US06445394B1
公开(公告)日：2002-09-03
申请号：US09212197
申请日：1998-12-15
申请人： Hugh Chow , Milivoje M. Aleksic , Adrian Hartog
发明人： Hugh Chow , Milivoje M. Aleksic , Adrian Hartog
IPC分类号： G09G539
CPC分类号： G06F3/1438 , G09G2360/127
摘要： A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.
摘要翻译：存储器系统和方法使用与例如与视频图形相关功能或其他合适功能不同的数据操作功能相关联的多个控制器的公共存储器。配置为时间分片器的多路复用器以第一速率通过第一总线选择用于与存储器传送的数据。多通道串行器通过多个第二总线耦合在多路复用器和多个控制器之间。每个第二总线与不同的通道相关联。多通道串行器具有用于多个第二总线中的每一个的串行器，其中每个串行器以与相应控制器相关联的第二速率传送与信道相关联的数据。

6. 发明授权

US06756988B1 Display FIFO memory management system 有权
标题翻译：显示FIFO存储器管理系统
公开(公告)号：US06756988B1
公开(公告)日：2004-06-29
申请号：US09369784
申请日：1999-08-06
申请人： Chun Wang , Raymond Li , Adrian Hartog , Daniel Gudmundson
发明人： Chun Wang , Raymond Li , Adrian Hartog , Daniel Gudmundson
IPC分类号： G09G536
CPC分类号： G06F5/10 , G09G5/395
摘要： A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.
摘要翻译：显示FIFO存储器管理系统和方法包括可编程FIFO模拟器，用于模拟显示FIFO存储器的漏极和填充时间，以在每个预定义的时钟周期自动预测显示FIFO存储器中剩余的寄存器数量。可编程定时器/计数器具有可编程精度，以适应显示屏显示模式的不同带宽，并用于确定剩余的条目数，以便仿真器可以适应不同的屏幕显示模式。 FIFO控制器根据可编程仿真器对显示FIFO中剩余寄存器条目数的预测，控制从存储器取出显示数据以填充显示FIFO存储器的定时。

7. 发明授权

US5946715A Page address space with varying page size and boundaries 失效
标题翻译：具有不同页面大小和边界的页面地址空间
公开(公告)号：US5946715A
公开(公告)日：1999-08-31
申请号：US311172
申请日：1994-09-23
申请人： Adrian Hartog , Sanford S. Lum , Fridtjof Martin Georg Weigel
发明人： Adrian Hartog , Sanford S. Lum , Fridtjof Martin Georg Weigel
IPC分类号： G06F12/06 , G09G5/39 , G06F12/00
CPC分类号： G06F12/0623 , G09G5/39
摘要： A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the page size, and reading or writing a page of data from or to the subsystem memory using the established aperture at consecutive memory locations beginning at one of the boundaries.
摘要翻译：一种寻址计算机子系统存储器的方法，包括建立具有预定页面大小的孔径，以定义页面大小的一半的倍数的地址边界寻址存储器，以及使用已建立的数据从子系统存储器读取或写入数据页面在从其中一个边界开始的连续记忆位置处的孔径。

8. 发明授权

US06344856B1 Text optimization 失效
标题翻译：文本优化
公开(公告)号：US06344856B1
公开(公告)日：2002-02-05
申请号：US08425741
申请日：1995-04-20
申请人： Sanford S. Lum , Adrian Hartog , Fridtjof Martin Georg Weigel , Josh Grossman , Dan O. Gudmundson
发明人： Sanford S. Lum , Adrian Hartog , Fridtjof Martin Georg Weigel , Josh Grossman , Dan O. Gudmundson
IPC分类号： G09G500
CPC分类号： G09G5/393 , G09G5/024 , G09G5/363
摘要： A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.
摘要翻译：一种提供用于在处理器控制的设备中显示的文本数据的方法，包括：以包装的单色位图形式存储定义文本字符的数据，寻址存储器以读取文本字符数据，将文本字符提供给图形处理器电路，在提供颜色属性的同时对文本字符的每一位进行比特操作，以及存储具有用于后续显示的颜色属性的打包文本字符。

9. 发明授权

US5953020A Display FIFO memory management system 失效
标题翻译：显示FIFO存储器管理系统
公开(公告)号：US5953020A
公开(公告)日：1999-09-14
申请号：US885248
申请日：1997-06-30
申请人： Chun Wang , Raymond Li , Adrian Hartog , Daniel Gudmundson
发明人： Chun Wang , Raymond Li , Adrian Hartog , Daniel Gudmundson
IPC分类号： G06F5/10 , G09G5/395 , G09G5/00
CPC分类号： G06F5/10 , G09G5/395
摘要： A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.
摘要翻译：显示FIFO存储器管理系统和方法包括可编程FIFO模拟器，用于模拟显示FIFO存储器的漏极和填充时间，以在每个预定义的时钟周期自动预测显示FIFO存储器中剩余的寄存器数量。可编程定时器/计数器具有可编程精度，以适应显示屏显示模式的不同带宽，并用于确定剩余的条目数，以便仿真器可以适应不同的屏幕显示模式。 FIFO控制器根据可编程仿真器对显示FIFO中剩余寄存器条目数的预测，控制从存储器取出显示数据以填充显示FIFO存储器的定时。

10. 发明授权

US06184906B2 Multiple pipeline memory controller for servicing real time data 失效
标题翻译：多管道存储器控制器，用于实时数据的维护
公开(公告)号：US06184906B2
公开(公告)日：2001-02-06
申请号：US08885335
申请日：1997-06-30
申请人： Chun Wang , Raymond Li , Adrian Hartog , Daniel Gudmundson
发明人： Chun Wang , Raymond Li , Adrian Hartog , Daniel Gudmundson
IPC分类号： G06F1316
CPC分类号： G09G5/001 , G06F3/14 , G06F13/1615 , G09G5/363 , G09G2340/0407 , G09G2340/125
摘要： A multiple pipeline memory controller has a plurality of two stage pipeline processors dedicated to separately process real time video capture and display refresh input request signals. A separate pipeline processor processes non-real time input signals. The multiple pipeline design reduces memory access latency and improves throughput of data in display FIFO memory to effect improved resolution. The multiple pipeline memory controller can be integrated in a video graphics controller (VGC).
摘要翻译：多管道存储器控制器具有专用于分别处理实时视频捕获和显示刷新输入请求信号的多个两级流水线处理器。单独的流水线处理器处理非实时输入信号。多管道设计减少了存储器访问延迟并提高了显示FIFO存储器中的数据吞吐量，从而提高了分辨率。多管道存储器控制器可以集成在视频图形控制器（VGC）中。

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