会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明授权
    • Far end resistance tracking design with near end pre-charge control for faster recovery time
    • 远端电阻跟踪设计,具有近端预充电控制,可实现更快的恢复时间
    • US08767494B2
    • 2014-07-01
    • US13493118
    • 2012-06-11
    • Chen-Lin YangChung-Yi WuYu-Hao Hsu
    • Chen-Lin YangChung-Yi WuYu-Hao Hsu
    • G11C7/00G11C8/00
    • G11C7/12G11C7/227G11C8/18G11C11/413
    • A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
    • 公开了一种字线追踪电路及相应的方法,包括具有与之相关联的阻抗特征的跟踪字线,其对存储器件中的一行存储单元进行建模,其中跟踪字线具有接近具有近似的字线脉冲信号的近端 结束上升脉冲沿和近端下降脉冲沿。 跟踪字线也有一个远端。 跟踪单元组件耦合到接收字线脉冲信号的跟踪字线的远端。 最后,电路包括耦合到跟踪单元的跟踪位线预充电电路,其被配置为使用近端字线脉冲信号对与跟踪单元相关联的跟踪位线进行预充电。
    • 10. 发明申请
    • POWER MANAGEMENT
    • 能源管理
    • US20110090753A1
    • 2011-04-21
    • US12885826
    • 2010-09-20
    • Cheng Hung LEEChung-Yi WUHsu-Shun CHENChung-Ji LU
    • Cheng Hung LEEChung-Yi WUHsu-Shun CHENChung-Ji LU
    • G11C5/14
    • G11C11/413
    • An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.
    • SRAM包括被配置用于使用不同的电压电平在不同的操作模式下工作的电路,其中基于操作模式调节电压电平和因此的电流泄漏。 例如,在正常工作模式下,SRAM将作为其他SRAM消耗电力。 在深度睡眠模式下,SRAM宏中的位单元的电源电压(例如,VDDI)降低SRAM电源电压(例如VDD)的约20-40%,足以将数据保留在位单元中。 当不需要访问SRAM时,SRAM在睡眠模式下运行,消耗很少或没有电源。