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    • 1. 发明申请
    • HIGH LINEAR FAST PEAK DETECTOR
    • 高线性快速探测器
    • WO2011031540A2
    • 2011-03-17
    • PCT/US2010046915
    • 2010-08-27
    • QUALCOMM INCSU WENJUNHADJICHRISTOS ARISTOTELECASSIA MARCONARATHONG CHIEWCHARN
    • SU WENJUNHADJICHRISTOS ARISTOTELECASSIA MARCONARATHONG CHIEWCHARN
    • G01R19/04
    • G01R19/04
    • A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.
    • 描述具有可变偏置电流和/或可变偏置电压的高线性快速峰值检测器。 在示例性设计中,峰值检测器包括晶体管,可变电流源,电容器和反馈电路。 晶体管接收输入信号并提供源极电流。 可变电流源接收输入信号,当输入信号为低电平时提供高偏置电流,并且当输入信号为高电平时提供低偏置电流。 当输入信号为高电平时,电容器由电源电流充电,当输入信号为低电平时,电容器被高偏置电流放电。 当输入信号为高电平时,反馈电路接收来自电容器的检测信号,并为晶体管提供更高的偏置电压,这导致来自晶体管的较高的源极电流。
    • 2. 发明申请
    • LEVEL SHIFTERS AND HIGH VOLTAGE LOGIC CIRCUITS
    • 水平变压器和高压逻辑电路
    • WO2011011639A2
    • 2011-01-27
    • PCT/US2010/042968
    • 2010-07-22
    • QUALCOMM INCORPORATEDCASSIA, Marco
    • CASSIA, Marco
    • H03K3/356H03K19/0185
    • H03K3/35613H03K19/018528
    • Level shifters and high voltage logic circuits implemented with MOS transistors having a low breakdown voltage relative to the voltage swing of the input and output signals are described. In an exemplary design, a level shifter includes a driver circuit and a latch. The driver circuit receives an input signal having a first voltage range and provides a drive signal having a second voltage range. The first and second voltage ranges may cover positive and negative voltages or different ranges of positive voltages. The latch receives the drive signal and provides an output signal having the second voltage range. The driver circuit may generate a control signal having a full voltage range based on the input signal and may then generate the drive signal based on the control signal. The level shifter may be used to implement a high voltage logic circuit.
    • 描述了相对于输入和输出信号的电压摆幅具有低击穿电压的MOS晶体管实现的电平移位器和高电压逻辑电路。 在示例性设计中,电平移位器包括驱动器电路和锁存器。 驱动电路接收具有第一电压范围的输入信号,并提供具有第二电压范围的驱动信号。 第一和第二电压范围可以覆盖正电压或负电压或不同的正电压范围。 锁存器接收驱动信号并提供具有第二电压范围的输出信号。 驱动器电路可以基于输入信号产生具有全电压范围的控制信号,然后可以基于控制信号产生驱动信号。 电平移位器可以用于实现高压逻辑电路。
    • 3. 发明申请
    • METHODS AND APPARATUSES FOR SELECTABLE VOLTAGE SUPPLY
    • 用于选择电压供应的方法和装置
    • WO2009061835A2
    • 2009-05-14
    • PCT/US2008082504
    • 2008-11-05
    • QUALCOMM INCCASSIA MARCOHADJICHRISTOS ARISTOTELEDONOVAN CONORLEE SANG-OH
    • CASSIA MARCOHADJICHRISTOS ARISTOTELEDONOVAN CONORLEE SANG-OH
    • H03K17/693H03K17/0814H03K17/16
    • H03K17/693Y10T307/696Y10T307/747
    • A circuit which selects a supply voltage from a plurality of voltage supplies is presented. The circuit includes a first transistor configured to select a first voltage supply, a second transistor configured to select a second voltage supply, a first parasitic current inhibitor coupled the first transistor, the first voltage supply, and the second voltage supply, where the first parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the first transistor, and a second parasitic current inhibitor coupled the second transistor, the first voltage supply, and the second voltage supply, where the second parasitic current inhibitor automatically utilizes the voltage supply providing the highest voltage for preventing a substrate current from flowing through a bulk node of the second transistor.
    • 提出了从多个电压源中选择电源电压的电路。 该电路包括:第一晶体管,被配置为选择第一电压源;第二晶体管,被配置为选择第二电压源;耦合第一晶体管,第一电压源和第二电压源的第一寄生电流抑制器,其中第一寄生 电流抑制器自动地利用提供最高电压的电压源来防止衬底电流流过第一晶体管的体节点,以及耦合第二晶体管,第一电压源和第二电压源的第二寄生电流抑制器,其中 第二寄生电流抑制器自动利用提供最高电压的电压源来防止衬底电流流过第二晶体管的体节点。
    • 7. 发明申请
    • SWITCHES WITH VARIABLE CONTROL VOLTAGES
    • 开关具有可变的控制电压
    • WO2011014582A3
    • 2011-05-26
    • PCT/US2010043593
    • 2010-07-28
    • QUALCOMM INCCASSIA MARCO
    • CASSIA MARCO
    • H03K17/06H03K17/0812
    • H03K17/693H03K17/08122H03K17/102H03K2017/066H03K2217/0054
    • Switches with variable control voltages and having improved reliability and performance are described. In an exemplary design, an apparatus includes a switch, a peak voltage detector, and a control voltage generator. The switch may be implemented with stacked transistors. The peak voltage detector detects a peak voltage of an input signal provided to the switch. In an exemplary design, the control voltage generator generates a variable control voltage to turn off the switch based on the detected peak voltage. In another exemplary design, the control voltage generator generates a variable control voltage to turn on the switch based on the detected peak voltage. In yet another exemplary design, the control voltage generator generates a control voltage to turn on the switch and attenuate the input signal when the peak voltage exceeds a high threshold.
    • 描述了具有可变控制电压并具有改进的可靠性和性能的开关。 在示例性设计中,装置包括开关,峰值电压检测器和控制电压发生器。 开关可以用堆叠的晶体管来实现。 峰值电压检测器检测提供给开关的输入信号的峰值电压。 在示例性设计中,控制电压生成器基于检测到的峰值电压生成可变控制电压以关闭开关。 在另一示例性设计中,控制电压生成器基于检测到的峰值电压生成可变控制电压以导通开关。 在又一个示例性设计中,当峰值电压超过高阈值时,控制电压发生器产生控制电压以导通开关并衰减输入信号。
    • 10. 发明申请
    • SEPARATE I AND Q BASEBAND PREDISTORTION IN DIRECT CONVERSION TRANSMITTERS
    • 直接转换发射机中的分离I和Q基带预测
    • WO2011072309A1
    • 2011-06-16
    • PCT/US2011/021213
    • 2011-01-13
    • QUALCOMM INCORPORATEDVERMA, SumitCASSIA, MarcoBANISTER, Brian Clarke
    • VERMA, SumitCASSIA, MarcoBANISTER, Brian Clarke
    • H04L27/36
    • H04L27/367
    • In-Phase (I) and Quadrature (Q) signals passing from a modem into a direct conversion transmitter are predistorted separately from, and independently of, one another. The I signal is predistorted to compensate for nonlinearities in the baseband I path circuitry between the modem and the upconverter. The Q signal is predistorted to compensate for nonlinearities in the baseband Q path circuitry between the modem and the upconverter. By employing the separate I and Q path baseband predistortion method, 4FMOD power in the upconverted and amplified signal as supplied to the transmitter antenna is reduced or eliminated. In one example, the transmitter employs single sideband modulation in the 777-787 MHz Verizon Band 13 while transmitting 23 dBm in a single LTE RB without emitting more than -57dBm/6.25kHz 4FMOD power into a nearby 763-775 MHz public safety band that starts only two megahertz away from the lower bound of Band 13.
    • 从调制解调器传送到直接转换发射机的同相(I)和正交(Q)信号彼此独立地进行预失真。 I信号被预失真以补偿调制解调器和上变频器之间的基带I路径电路中的非线性。 Q信号被预失真以补偿调制解调器和上变频器之间的基带Q路径电路中的非线性。 通过采用单独的I和Q路径基带预失真方法,降低或消除了提供给发射机天线的上变频和放大信号中的4FMOD功率。 在一个示例中,发射机在777-787MHz Verizon Band 13中采用单边带调制,同时在单个LTE RB中传输23 dBm,而不会在附近的763-775 MHz公共安全频段发射超过-57dBm / 6.25kHz的4FMOD功率, 距离13号带的下限仅开始两兆。