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1. 发明申请

WO2011008562A3 INTEGRATED POWER AMPLIFIER WITH LOAD INDUCTOR LOCATED UNDER IC DIE 审中-公开
公开(公告)号：WO2011008562A3
公开(公告)日：2011-01-20
申请号：PCT/US2010/040488
申请日：2010-06-29
申请人： QUALCOMM Incorporated , KLEMENS, Guy , MYERS, Thomas A. , FREDERICK, JR., Norman L. , ZHAO, Yu , NEJATI, Babak , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele
发明人： KLEMENS, Guy , MYERS, Thomas A. , FREDERICK, JR., Norman L. , ZHAO, Yu , NEJATI, Babak , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele
IPC分类号： H01L23/64 , H03F3/195
摘要： A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

2. 发明申请

WO2010068504A2 LINEAR AND POLAR DUAL MODE TRANSMITTER CIRCUIT 审中-公开
标题翻译：线性和极性双模发射机电路
公开(公告)号：WO2010068504A2
公开(公告)日：2010-06-17
申请号：PCT/US2009/065962
申请日：2009-11-25
申请人： QUALCOMM Incorporated , ANIRUDDHAN, Sankaran , NARATHONG, Chiewcharn , SRIDHARA, Ravi , NEJATI, Babak
发明人： ANIRUDDHAN, Sankaran , NARATHONG, Chiewcharn , SRIDHARA, Ravi , NEJATI, Babak
IPC分类号： H03D7/16
CPC分类号： H03C5/00 , H03C3/40 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/1491 , H03D7/165 , H03D7/166 , H03D2200/0023 , H03D2200/0084 , H03G3/3042 , H04L27/34 , H04L27/36 , H04L27/361 , H04L27/362 , H04L27/38 , H04L27/389
摘要： Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.
摘要翻译：用于配置发射机电路以支持线性或极坐标模式的方法和装置。在线性模式中，通过调整同相（I）和正交（Q）信号的幅度来指定基带信号，而在极坐标模式中，通过调整本地振荡器（LO）的相位来指定信息信号，信号和I或Q信号的振幅。在示例性实施例中，为线性模式和极坐标模式提供了两个混合器，一组开关基于装置是以线性模式还是极坐标模式选择提供给混合器之一的适当输入信号。在示例性实施例中，可以使用可升级架构来实现每个混合器，所述可扩展架构基于所需的发射功率有效地调整混频器

3. 发明申请

WO2011022549A2 DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT 审中-公开
标题翻译：数字可调节的级间匹配电路
公开(公告)号：WO2011022549A2
公开(公告)日：2011-02-24
申请号：PCT/US2010/046021
申请日：2010-08-19
申请人： QUALCOMM INCORPORATED , ZHAO, Yu , NEJATI, Babak , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele
发明人： ZHAO, Yu , NEJATI, Babak , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele
IPC分类号： H03H7/38
CPC分类号： H03F1/42 , H03F1/223 , H03F3/193 , H03F2200/318 , H03H7/40
摘要： A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.
摘要翻译：描述了可以提高性能的可调节级间匹配电路。在示例性设计中，装置包括耦合在第一和第二有源电路之间的第一有源电路（例如，驱动器放大器），第二有源电路（例如功率放大器）以及可调谐的级间匹配电路。可调级间匹配电路包括可调电容器，该可调电容器可以在离散步骤中变化以调整第一和第二有源电路之间的阻抗匹配。在示例性设计中，可调电容器包括（i）并联耦合的多个电容器和（ii）耦合到多个电容器的多个开关，每个电容器一个开关。每个开关可以打开以选择关联的电容器或关闭以取消选择关联的电容器。可调电容器还可以包括与多个电容器并联耦合的固定电容器。

4. 发明申请

WO2010135709A1 OUTPUT CIRCUIT WITH INTEGRATED IMPEDANCE MATCHING, POWER COMBINING AND FILTERING FOR POWER AMPLIFIERS AND OTHER CIRCUITS 审中-公开
标题翻译：具有集成阻抗匹配的输出电路，功率放大器和其他电路的功率组合和滤波
公开(公告)号：WO2010135709A1
公开(公告)日：2010-11-25
申请号：PCT/US2010/035861
申请日：2010-05-21
申请人： QUALCOMM INCORPORATED , KLEMENS, Guy , PLETCHER, Nathan, M. , NEJATI, Babak , FREDERICK, Jr., Norman, L. , MYERS, Thomas, A.
发明人： KLEMENS, Guy , PLETCHER, Nathan, M. , NEJATI, Babak , FREDERICK, Jr., Norman, L. , MYERS, Thomas, A.
IPC分类号： H03H7/38 , H03H7/48 , H03F3/60 , H03F1/56 , H04B1/04
CPC分类号： H03H7/38 , H03F1/56 , H03F3/195 , H03F3/245 , H03F3/604 , H03F2200/108 , H03F2200/171 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/451 , H03H7/48 , H04B1/0483
摘要： An output circuit with integrated impedance matching, power combining, and filtering and suitable for use with power amplifiers and other circuits is described. In an exemplary design, an apparatus may include first and second circuits (e.g., power amplifiers) and an output circuit. The first circuit may provide a first single-ended signal and may have a first output impedance. The second circuit may provide a second single-ended signal and may have a second output impedance. The output circuit may include (i) first and second matching circuits that perform output impedance matching and filtering for the first and second circuits, (ii) a combiner (e.g., a summing node) that combines the first and second single-ended signals to obtain a combined single-ended signal, (iii) a third matching circuit that performs impedance matching and filtering for the combined single-ended signal, and (iv) switches to route the single-ended signals to different outputs.
摘要翻译：描述了具有集成阻抗匹配，功率组合和滤波并适用于功率放大器和其他电路的输出电路。在示例性设计中，装置可以包括第一和第二电路（例如，功率放大器）和输出电路。第一电路可以提供第一单端信号并且可以具有第一输出阻抗。第二电路可以提供第二单端信号并且可以具有第二输出阻抗。输出电路可以包括（i）对第一和第二电路执行输出阻抗匹配和滤波的第一和第二匹配电路，（ii）将第一和第二单端信号组合到的组合器（例如，求和节点）获得组合的单端信号，（iii）对组合的单端信号执行阻抗匹配和滤波的第三匹配电路，以及（iv）将单端信号路由到不同输出的开关。

5. 发明申请

WO2011011757A1 POWER AMPLIFIER WITH SWITCHED OUTPUT MATCHING FOR MULTI-MODE OPERATION 审中-公开
标题翻译：具有多模操作的开关量输出匹配功率放大器
公开(公告)号：WO2011011757A1
公开(公告)日：2011-01-27
申请号：PCT/US2010/043156
申请日：2010-07-23
申请人： QUALCOMM Incorporated , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele , ZHAO, Yu , NEJATI, Babak
发明人： PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele , ZHAO, Yu , NEJATI, Babak
IPC分类号： H04B1/04 , H03F1/56
CPC分类号： H04B1/0458 , H03F1/56 , H03F3/245 , H04B1/406
摘要： Exemplary embodiments are directed to a transmitter with a power amplifier and a switched output matching circuit implementing a plurality of output paths for a plurality of operating modes is described. The power amplifier receives an input RF signal and provides an amplified RF signal. An output matching network performs impedance transformation from low impedance at the power amplifier output to higher impedance at the matching network output. The plurality of output paths are coupled to the output matching network. Each output path provides a different target output impedance for the power amplifier and routes the amplified RF signal from the power amplifier to an antenna when that output path is selected. Each output path may include a matching network coupled in series with a switch. The matching network provides the target output impedance for the power amplifier when the output path is selected. The switch couples or decouples the output path to/from the power amplifier.
摘要翻译：示例性实施例涉及具有功率放大器和实现用于多个操作模式的多个输出路径的切换输出匹配电路的发射机。功率放大器接收输入RF信号并提供放大的RF信号。输出匹配网络执行从功率放大器输出端的低阻抗到匹配网络输出端的较高阻抗的阻抗变换。多个输出路径耦合到输出匹配网络。当选择该输出路径时，每个输出路径为功率放大器提供不同的目标输出阻抗，并将放大的RF信号从功率放大器路由到天线。每个输出路径可以包括与开关串联耦合的匹配网络。当选择输出路径时，匹配网络为功率放大器提供目标输出阻抗。开关将输出路径耦合到/从功率放大器解耦。

6. 发明申请

WO2011008562A2 INTEGRATED POWER AMPLIFIER WITH LOAD INDUCTOR LOCATED UNDER IC DIE 审中-公开
标题翻译：集成功率放大器与负载电感位于IC DIE下
公开(公告)号：WO2011008562A2
公开(公告)日：2011-01-20
申请号：PCT/US2010040488
申请日：2010-06-29
申请人： QUALCOMM INC , KLEMENS GUY , MYERS THOMAS A , FREDERICK JR NORMAN L , ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
发明人： KLEMENS GUY , MYERS THOMAS A , FREDERICK JR NORMAN L , ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
IPC分类号： H01L23/64 , H03F3/195
CPC分类号： H03F3/195 , H01L23/645 , H01L23/66 , H01L2223/6655 , H01L2223/6661 , H01L2224/16225 , H01L2924/00014 , H01L2924/1305 , H01L2924/19015 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.
摘要翻译：这里描述了紧凑的集成功率放大器。在示例性设计中，装置包括（i）具有用于功率放大器的至少一个晶体管的集成电路（IC）管芯，以及（ii）具有用于功率放大器的负载电感器的IC封装。 IC芯片安装在IC封装上，晶体管位于负载感应器上方。在示例性设计中，IC管芯包括放置在IC封装上的负载电感器上的晶体管歧管。晶体管制造在晶体管歧管中，在晶体管歧管的中心具有漏极连接，并且在晶体管歧管的两侧具有源极连接。 IC芯片和IC封装可以包括一个或多个附加的功率放大器。每个功率放大器的晶体管可以位于该功率放大器的负载电感上。

7. 发明申请

WO2011017463A1 AMPLIFIER MODULE WITH MULTIPLE OPERATING MODES 审中-公开
标题翻译：具有多种操作模式的放大器模块
公开(公告)号：WO2011017463A1
公开(公告)日：2011-02-10
申请号：PCT/US2010/044461
申请日：2010-08-04
申请人： QUALCOMM INCORPORATED , PLETCHER, Nathan, M. , HADJICHRISTOS, Aristotele , NEJATI, Babak
发明人： PLETCHER, Nathan, M. , HADJICHRISTOS, Aristotele , NEJATI, Babak
IPC分类号： H03F1/02 , H03F3/195 , H03F3/21 , H03F3/24 , H03F3/72 , H03F1/56
CPC分类号： H03F1/0277 , H03F1/56 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/72 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/451 , H03F2200/522 , H03F2200/75 , H03F2203/21136 , H03F2203/21139 , H03F2203/21142 , H03F2203/21157 , H03F2203/21175 , H03F2203/21196 , H03F2203/7206 , H03F2203/7236 , H03G1/0088
摘要： An amplifier module with multiple operating modes is described. In an exemplary design, the amplifier module includes an amplifier (e.g., a power amplifier), a switch, and an output circuit. The amplifier receives and amplifies an input signal and provides an amplified signal in a first mode. The switch is coupled to the output of the amplifier and bypasses the amplifier and provides a bypass signal in a second mode. The output circuit is coupled to the amplifier and the switch. The output circuit performs output impedance matching for the amplifier in the first mode. The output circuit also (i) receives the amplified signal and provides an output signal in the first mode and (ii) receives the bypass signal and provides the output signal in the second mode. The amplifier is enabled in the first mode and disabled in the second mode.
摘要翻译：描述具有多种工作模式的放大器模块。在示例性设计中，放大器模块包括放大器（例如，功率放大器），开关和输出电路。放大器接收并放大输入信号并在第一模式中提供放大的信号。开关耦合到放大器的输出端，并且旁路放大器并在第二模式中提供旁路信号。输出电路耦合到放大器和开关。输出电路在第一模式下对放大器执行输出阻抗匹配。输出电路还（i）接收放大的信号并在第一模式中提供输出信号，并且（ii）接收旁路信号并在第二模式中提供输出信号。放大器在第一种模式下使能，在第二种模式下禁用。

8. 发明申请

WO2010068504A3 LINEAR AND POLAR DUAL MODE TRANSMITTER CIRCUIT 审中-公开
标题翻译：线性和极性双模式发射机电路
公开(公告)号：WO2010068504A3
公开(公告)日：2010-08-19
申请号：PCT/US2009065962
申请日：2009-11-25
申请人： QUALCOMM INC , ANIRUDDHAN SANKARAN , NARATHONG CHIEWCHARN , SRIDHARA RAVI , NEJATI BABAK
发明人： ANIRUDDHAN SANKARAN , NARATHONG CHIEWCHARN , SRIDHARA RAVI , NEJATI BABAK
IPC分类号： H03C3/40 , H03C5/00 , H04L27/36
CPC分类号： H03C5/00 , H03C3/40 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/1491 , H03D7/165 , H03D7/166 , H03D2200/0023 , H03D2200/0084 , H03G3/3042 , H04L27/34 , H04L27/36 , H04L27/361 , H04L27/362 , H04L27/38 , H04L27/389
摘要： Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.
摘要翻译：用于配置发射机电路以支持线性或极性模式的方法和设备。在线性模式中，通过调整同相（I）和正交（Q）信号的幅度来指定基带信号，而在极性模式中，通过调整本地振荡器（LO）的相位来指定信息信号，信号和I或Q信号的幅度。在示例性实施例中，为线性模式和极性模式提供两个混频器，其中一组开关基于设备是以线性还是极性模式工作来选择提供给混频器之一的适当输入信号。在示例性实施例中，可以使用基于所需发射功率有效地调整混频器大小的可扩展架构来实现每个混频器。

9. 发明申请

WO2011022549A3 DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT 审中-公开
标题翻译：数字可调节间歇匹配电路
公开(公告)号：WO2011022549A3
公开(公告)日：2011-04-21
申请号：PCT/US2010046021
申请日：2010-08-19
申请人： QUALCOMM INC , ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
发明人： ZHAO YU , NEJATI BABAK , PLETCHER NATHAN M , HADJICHRISTOS ARISTOTELE
IPC分类号： H03H7/38 , H03F1/42 , H03F3/00 , H03F3/193
CPC分类号： H03F1/42 , H03F1/223 , H03F3/193 , H03F2200/318 , H03H7/40
摘要： A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.
摘要翻译：描述了可以提高性能的可调谐级间匹配电路。在示例性设计中，装置包括耦合在第一和第二有源电路之间的第一有源电路（例如，驱动器放大器），第二有源电路（例如，功率放大器）和可调谐级间匹配电路。可调谐级间匹配电路包括可以在离散步骤中变化的可调谐电容器，以调整第一和第二有源电路之间的阻抗匹配。在示例性设计中，可调谐电容器包括（i）并联耦合的多个电容器和（ii）耦合到多个电容器的多个开关，用于每个电容器的一个开关。每个开关可以被接通以选择一个相关联的电容器或关闭以取消选择相关联的电容器。可调谐电容器还可以包括与多个电容器并联耦合的固定电容器。

10. 发明申请

WO2011017368A1 MULTI-STAGE IMPEDANCE MATCHING 审中-公开
标题翻译：多级阻抗匹配
公开(公告)号：WO2011017368A1
公开(公告)日：2011-02-10
申请号：PCT/US2010/044306
申请日：2010-08-03
申请人： QUALCOMM INCORPORATED , NEJATI, Babak , ZHAO, Yu , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele , SEE, Puay Hoe
发明人： NEJATI, Babak , ZHAO, Yu , PLETCHER, Nathan M. , HADJICHRISTOS, Aristotele , SEE, Puay Hoe
IPC分类号： H03F1/56 , H03F3/72
CPC分类号： H03F1/565 , H03F3/211 , H03F3/72
摘要： Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.
摘要翻译：描述了用于执行阻抗匹配的示例性技术。在示例性实施例中，该装置可以包括耦合到第一和第二匹配电路的放大器（例如功率放大器）。第一匹配电路可以包括耦合到第一节点的多个级并且可以为放大器提供输入阻抗匹配。第二匹配电路可以包括耦合到第二节点的多个级并且可以为放大器提供输出阻抗匹配。至少一个开关可以耦合在第一和第二节点之间，并且可以旁路或选择放大器。第一和第二节点可以具有公共阻抗。该装置还可以包括与放大器并联并且进一步耦合到匹配电路的第二放大器。第二匹配电路可以包括耦合到放大器的第一输入级，耦合到第二放大器的第二输入级，以及经由开关耦合到两个输入级的第二级。

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