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1. 发明申请

US20140141610A1 NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME 有权
标题翻译：包括垂直NAND条的非易失性存储器件及其形成方法
公开(公告)号：US20140141610A1
公开(公告)日：2014-05-22
申请号：US14164712
申请日：2014-01-27
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

2. 发明申请

US20100270689A1 Semiconductor packages and electronic systems including the same 有权
标题翻译：半导体封装和电子系统包括相同的
公开(公告)号：US20100270689A1
公开(公告)日：2010-10-28
申请号：US12659775
申请日：2010-03-22
申请人： Hye-jin Kim , Byung-seo Kim , Sun-il Youn
发明人： Hye-jin Kim , Byung-seo Kim , Sun-il Youn
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/4911 , H01L2225/06506 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Provided are semiconductor packages and electronic systems including the same. A substrate is provided. A plurality of semiconductor chips may be stacked the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.
摘要翻译：提供半导体封装和包括其的电子系统。提供基板。多个半导体芯片可以堆叠在基板上，并且它们中的每一个可以包括至少一个电极焊盘。多个半导体芯片中的至少一个可以包括被配置为与至少一个电极焊盘电连接的至少一个再分布焊盘。

3. 发明申请

US20090168493A1 SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储器单元的方法
公开(公告)号：US20090168493A1
公开(公告)日：2009-07-02
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00 , H01L21/00 , H01L47/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

4. 发明申请

US20090020820A1 CHANNEL-STRESSED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION 有权
标题翻译：通道应力半导体器件和制造方法
公开(公告)号：US20090020820A1
公开(公告)日：2009-01-22
申请号：US12138502
申请日：2008-06-13
申请人： Hion-suck BAIK , Jong-bong PARK , Jung-yun WON , Hwa-sung RHEE , Byung-seo KIM , Ho LEE , Myung-sun KIM , Ji-hye YI
发明人： Hion-suck BAIK , Jong-bong PARK , Jung-yun WON , Hwa-sung RHEE , Byung-seo KIM , Ho LEE , Myung-sun KIM , Ji-hye YI
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在PMOS器件的外延源极/漏极区域上形成至少一个覆盖层，在包括至少一个覆盖层并且在相邻的NMOS器件上的PMOS器件上形成应力记忆（SM）层，以及处理SM 形成在NMOS和PMOS器件上的层，以在NMOS器件的沟道区域中引起拉伸应力。

5. 发明申请

US20080291652A1 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME, PRINTED CIRCUIT BOARD, AND ELECTRONIC DEVICE 有权
标题翻译：半导体封装及其形成方法，印刷电路板和电子器件
公开(公告)号：US20080291652A1
公开(公告)日：2008-11-27
申请号：US12124915
申请日：2008-05-21
申请人： Mu-Seob Shin , Byung-Seo Kim , Min-Young Son , Min-Keun Kwak
发明人： Mu-Seob Shin , Byung-Seo Kim , Min-Young Son , Min-Keun Kwak
IPC分类号： H05K7/00
CPC分类号： H01L21/565 , H01L23/3128 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/105 , H01L2224/05553 , H01L2224/06136 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/078 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess.
摘要翻译：提供一种半导体封装及其形成方法，以及PCB（印刷电路板）。所述半导体封装包括：PCB，其在其大致中央部分包括狭缝，所述PCB包括上表面和下表面; 安装在PCB的上表面上的半导体芯片; 上模制层，设置在上表面并覆盖半导体芯片; 以及填充所述狭缝并覆盖所述PCB的下表面的一部分的下成型层，其中所述PCB包括在其侧表面处的连接凹部，并且所述上成型层和所述下成型层彼此接触连接凹槽。

6. 发明授权

US07453794B2 Channel estimation and synchronization with preamble using polyphase code 失效
标题翻译：使用多相码的信道估计和前同步码同步
公开(公告)号：US07453794B2
公开(公告)日：2008-11-18
申请号：US10737339
申请日：2003-12-16
申请人： Yuguang Fang , Byung-Seo Kim
发明人： Yuguang Fang , Byung-Seo Kim
IPC分类号： H04J11/00
CPC分类号： H04L27/2656 , H04L5/0007 , H04L5/0048 , H04L25/0204 , H04L25/0226 , H04L27/2605 , H04L27/2613 , H04L27/2662
摘要： A preamble for an OFDM signal synchronizes (104) and estimates (106) the sub-channels with only one code. One polyphase code sequence is used repeatedly for the preamble. The preamble is spread out over the bandwidth, which is the same as an OFDM symbol in the frequency domain and has good autocorrelation characteristics in the time domain. All OFDM signals are added with this preamble at the beginning of the OFDM signal and transmitted on the channel at a transmitter (50). At the receiving end, the receiver (100) first does the autocorrelation process to find out a peak value for synchronization in the time domain. Then, since the polyphase code is known at the receiver, the signal to noise ratio for each sub-carrier is calculated in the frequency domain and smoothed using the normal (Gaussian) distribution to provide the channel estimation. Since the synchronization and channel estimation are processed with a single preamble, the overhead for these two functions is significantly reduced.
摘要翻译： OFDM信号的前导码同步（104）并仅使用一个码估计（106）子信道。对于前同步码重复使用一个多相码序列。前导码在带宽上扩展，与频域中的OFDM符号相同，并且在时域中具有良好的自相关特性。所有OFDM信号在OFDM信号的开始处与该前同步码相加，并在发射机（50）的信道上发送。在接收端，接收机（100）首先进行自相关处理，以找出在时域中同步的峰值。然后，由于在接收机处已知多相码，所以在频域中计算每个子载波的信噪比并使用正态（高斯）分布进行平滑，以提供信道估计。由于使用单个前同步码来处理同步和信道估计，所以这两个功能的开销显着降低。

7. 发明授权

US08971118B2 Methods of forming non-volatile memory devices including vertical NAND strings 有权
标题翻译：形成包括垂直NAND串的非易失性存储器件的方法
公开(公告)号：US08971118B2
公开(公告)日：2015-03-03
申请号：US14164712
申请日：2014-01-27
申请人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
发明人： Beom-jun Jin , Byung-seo Kim , Sung-Dong Kim
IPC分类号： G11C16/04 , G11C16/06 , H01L21/28 , H01L27/115 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/308 , H01L21/76802 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11578
摘要： A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
摘要翻译：基于NAND的非易失性存储器件可以包括垂直地布置为NAND串的多个存储单元和多个字线板，每个字线板电连接到NAND串中的存储器单元的相应栅极。多个字线触点可以各自电连接到相应的字线板，其中多个字线触点与器件中的位线方向对准。

8. 发明授权

US08643193B2 Semiconductor packages and electronic systems including the same 有权
公开(公告)号：US08643193B2
公开(公告)日：2014-02-04
申请号：US13630619
申请日：2012-09-28
申请人： Hye-Jin Kim , Byung-Seo Kim , Sunpil Youn
发明人： Hye-Jin Kim , Byung-Seo Kim , Sunpil Youn
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/4911 , H01L2225/06506 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

9. 发明申请

US20120175580A1 VARIABLE RESISTANCE MEMORY 审中-公开
标题翻译：可变电阻记忆
公开(公告)号：US20120175580A1
公开(公告)日：2012-07-12
申请号：US13430042
申请日：2012-03-26
申请人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong SONG , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

10. 发明授权

US07932102B2 Phase change memory and method of fabricating the same 失效
标题翻译：相变记忆及其制造方法
公开(公告)号：US07932102B2
公开(公告)日：2011-04-26
申请号：US12314884
申请日：2008-12-18
申请人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
发明人： Yoon-Jong Song , Byung-Seo Kim , Kyung-Chang Ryoo
IPC分类号： H01L21/00 , H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
摘要翻译：制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。

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