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1. 发明授权

US08179711B2 Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储单元的方法
公开(公告)号：US08179711B2
公开(公告)日：2012-05-15
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

2. 发明申请

US20090168493A1 SEMICONDUCTOR MEMORY DEVICE WITH STACKED MEMORY CELL AND METHOD OF MANUFACTURING THE STACKED MEMORY CELL 有权
标题翻译：具有堆叠存储单元的半导体存储器件和制造堆叠存储器单元的方法
公开(公告)号：US20090168493A1
公开(公告)日：2009-07-02
申请号：US12273225
申请日：2008-11-18
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00 , H01L21/00 , H01L47/00
CPC分类号： G11C13/003 , G11C5/02 , G11C7/18 , G11C11/15 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/71 , G11C2213/74 , G11C2213/79 , H01L27/24
摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

3. 发明授权

US07453716B2 Semiconductor memory device with stacked control transistors 有权
标题翻译：具有堆叠控制晶体管的半导体存储器件
公开(公告)号：US07453716B2
公开(公告)日：2008-11-18
申请号：US11238381
申请日：2005-09-29
申请人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
发明人： Sung-min Kim , Eun-jung Yun , Jong-soo Seo , Du-eung Kim , Beak-hyung Cho , Byung-seo Kim
IPC分类号： G11C11/00
CPC分类号： H01L27/2436 , G11C13/0004 , G11C13/003 , G11C2213/74 , G11C2213/79
摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.
摘要翻译：在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。在一个示例中，控制晶体管的数量是两个。半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

4. 发明授权

US08129800B2 Gate-all-around integrated circuit devices 有权
标题翻译：全能集成电路器件
公开(公告)号：US08129800B2
公开(公告)日：2012-03-06
申请号：US11374644
申请日：2006-03-13
申请人： Eun-jung Yun , Sung-young Lee , Min-sang Kim , Sung-min Kim
发明人： Eun-jung Yun , Sung-young Lee , Min-sang Kim , Sung-min Kim
IPC分类号： H01L29/06
CPC分类号： H01L29/78696 , H01L29/42392
摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.
摘要翻译：栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。第一和第二源极/漏极区域与有源区域形成p-n整流结。沟道区域在第一和第二源极/漏极区域之间延伸。绝缘栅极围绕通道区域。

5. 发明申请

US20080233693A1 COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES INCLUDING A THIN-BODY CHANNEL AND DUAL GATE DIELECTRIC LAYERS AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：补充金属氧化物半导体（CMOS）器件，包括薄体通道和双栅介质层及其制造方法
公开(公告)号：US20080233693A1
公开(公告)日：2008-09-25
申请号：US12108304
申请日：2008-04-23
申请人： Sung-young Lee , Sung-min Kim , Sung-dae Suk , Eun-jung Yun
发明人： Sung-young Lee , Sung-min Kim , Sung-dae Suk , Eun-jung Yun
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823807 , H01L29/42384 , H01L29/42392 , H01L29/495 , H01L29/78696
摘要： A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.
摘要翻译：互补金属氧化物半导体（CMOS）器件包括具有硅外延层的NMOS薄体通道。 NMOS绝缘层形成在NMOS薄体通道的表面上并且包围NMOS薄体通道。在NMOS绝缘层上形成NMOS金属栅极。 CMOS器件还包括包括具有硅外延层的PMOS薄体通道的p沟道金属氧化物半导体（PMOS）晶体管。在PMOS薄体通道的表面上形成PMOS绝缘层。在PMOS绝缘层上形成PMOS金属栅极。所述NMOS绝缘层包括氧化硅层，所述PMOS绝缘层包括电子捕获层，所述NMOS绝缘层包括空穴俘获介电层，所述PMOS绝缘层包括氧化硅层，或所述NMOS绝缘层包括孔电介质层和PMOS绝缘层包括电子俘获电介质层。

6. 发明申请

US20070161168A1 Method for fabricating a semiconductor device having a multi-bridge-channel 审中-公开
标题翻译：一种具有多桥通道的半导体器件的制造方法
公开(公告)号：US20070161168A1
公开(公告)日：2007-07-12
申请号：US11710580
申请日：2007-02-26
申请人： Eun-jung Yun , Sung-min Kim , Sung-young Lee
发明人： Eun-jung Yun , Sung-min Kim , Sung-young Lee
IPC分类号： H01L21/337 , H01R4/60
CPC分类号： H01L29/66795 , H01L29/785
摘要： In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.
摘要翻译：在具有多桥通道的半导体器件及其制造方法中，该器件包括从半导体衬底的表面突出并分别具有源极和漏极区域的第一和第二半导体柱，其部分，连接第一和第二半导体柱的上侧部分的沟道半导体层，沟道半导体层和半导体衬底上的栅极绝缘层，围绕至少一部分沟道半导体层的栅极绝缘层，栅电极在所述栅绝缘层上包围所述沟道半导体层之间的区域的至少一部分，以及形成在所述沟道半导体层之间的接合辅助层，与所述栅电极层接触的所述结辅助层和所述第一和第二栅极的上侧部分半导体柱，并且具有与沟道半导体层相同的宽度。

7. 发明申请

US20060192249A1 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 审中-公开
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US20060192249A1
公开(公告)日：2006-08-31
申请号：US11396488
申请日：2006-04-03
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

8. 发明申请

US20050272231A1 Gate-all-around type of semiconductor device and method of fabricating the same 有权
标题翻译：全栅型半导体器件及其制造方法
公开(公告)号：US20050272231A1
公开(公告)日：2005-12-08
申请号：US11074711
申请日：2005-03-09
申请人： Eun-jung Yun , Sung-min Kim , Sung-young Lee
发明人： Eun-jung Yun , Sung-min Kim , Sung-young Lee
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/335 , H01L21/336 , H01L21/4763 , H01L29/423 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66772 , H01L29/78654
摘要： A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mono-crystalline silicon substrate, etching the substrate to form a pair of spaced-apart trenches such that a wall of the mono-crystalline silicon stands between the trenches, filling the trenches with insulative material, implanting impurities into the wall of mono-crystalline silicon, and forming an opening in the wall such that portions of the wall remain as pillars. A sacrificial layer is formed at the bottom of the opening. Then, the channel region is formed atop the sacrificial layer between the pillars. The sacrificial layer is subsequently removed and the gate oxide and gate electrode are formed around the channel region. One or more sidewall spacers are used to establish the effective width of the channel region and/or minimize parasitic capacitance between the source/drain regions and gate electrode.
摘要翻译：栅极全能（GAA）晶体管器件具有一对支柱，其包括源极/漏极区域，桥接源极/漏极区域的沟道区域以及围绕沟道区域的栅极电极和栅极氧化物。支柱通过提供单晶硅衬底形成，蚀刻衬底以形成一对隔开的沟槽，使得单晶硅的壁站立在沟槽之间，用绝缘材料填充沟槽，将杂质注入单晶硅的壁，并且在壁中形成开口，使得壁的一部分保持为支柱。牺牲层形成在开口的底部。然后，通道区域形成在支柱之间的牺牲层的顶部。随后去除牺牲层，并且在沟道区周围形成栅极氧化物和栅电极。使用一个或多个侧壁间隔物来建立沟道区域的有效宽度和/或最小化源极/漏极区域和栅电极之间的寄生电容。

9. 发明授权

US08835993B2 Gate-all-around integrated circuit devices 有权
标题翻译：全能集成电路器件
公开(公告)号：US08835993B2
公开(公告)日：2014-09-16
申请号：US13411699
申请日：2012-03-05
申请人： Eun-jung Yun , Sung-young Lee , Min-sang Kim , Sung-min Kim
发明人： Eun-jung Yun , Sung-young Lee , Min-sang Kim , Sung-min Kim
IPC分类号： H01L29/78 , H01L29/786 , H01L29/423
CPC分类号： H01L29/78696 , H01L29/42392
摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.
摘要翻译：栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。第一和第二源极/漏极区域与有源区域形成p-n整流结。沟道区域在第一和第二源极/漏极区域之间延伸。绝缘栅极围绕通道区域。

10. 发明申请

US20080128792A1 NON-VOLATILE MEMORY DEVICES INCLUDING DIVIDED CHARGE STORAGE STRUCTURES 失效
标题翻译：非易失性存储器件，包括分开的充电存储结构
公开(公告)号：US20080128792A1
公开(公告)日：2008-06-05
申请号：US12014276
申请日：2008-01-15
申请人： Sung-min Kim , Dong-won Kim , Eun-jung Yun
发明人： Sung-min Kim , Dong-won Kim , Eun-jung Yun
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.
摘要翻译：半导体存储器件包括其中具有第一和第二源极/漏极区域以及它们之间的沟道区域的衬底。该器件还包括沟道区上的第一和第二电荷存储层，位于第一和第二电荷存储层之间的沟道区上的第一绝缘层，以及与沟道区相对的绝缘层上的第一绝缘层，第一和第二电荷存储层。栅电极远离基板延伸超过第一和第二电荷存储层。该器件还包括从第一和第二电荷存储层的内侧壁相邻延伸的第二和第三绝缘层，沿栅电极的一部分延伸超过第一和第二电荷存储层。还讨论了相关的制造方法。

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