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1. 发明申请

US20080074143A1 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US20080074143A1
公开(公告)日：2008-03-27
申请号：US11888317
申请日：2007-07-30
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter Kazarian , Andrew Leaver , David Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter Kazarian , Andrew Leaver , David Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

2. 发明授权

US09298799B1 Method and apparatus for utilizing patterns in data to reduce file size 有权
公开(公告)号：US09298799B1
公开(公告)日：2016-03-29
申请号：US13620338
申请日：2012-09-14
申请人： Bruce Pedersen , Jim Park , Peter Kazarian
发明人： Bruce Pedersen , Jim Park , Peter Kazarian
IPC分类号： G06F17/30
CPC分类号： G06F17/30595 , H03M7/3079 , H03M7/3088 , H03M7/707
摘要： A method for managing records in an object-oriented database is disclosed. Modified representations of data in fields of records is generated in response to patterns in the data. The modified representations of the data is compressed utilizing similarities in the modified representations of the data.

3. 发明授权

US08356019B1 Method and apparatus for utilizing patterns in data to reduce file size 有权
标题翻译：利用数据中的图案来减少文件大小的方法和装置
公开(公告)号：US08356019B1
公开(公告)日：2013-01-15
申请号：US10316371
申请日：2002-12-11
申请人： Bruce Pedersen , Jim Park , Peter Kazarian
发明人： Bruce Pedersen , Jim Park , Peter Kazarian
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F17/30595 , H03M7/3079 , H03M7/3088 , H03M7/707
摘要： A method for managing records in an object-oriented database is disclosed. Modified representations of data in fields of records is generated in response to patterns in the data. The modified representations of the data is compressed utilizing similarities in the modified representations of the data.
摘要翻译：公开了一种用于管理面向对象数据库中的记录的方法。响应于数据中的模式生成记录字段中数据的修改表示。使用数据的修改表示中的相似性来压缩数据的修改表示。

4. 发明授权

US07302669B1 Method and software for generating enable and data input signals for flip-flops used for implementing logic functions on programmable logic devices 有权
标题翻译：用于产生用于在可编程逻辑器件上实现逻辑功能的触发器的使能和数据输入信号的方法和软件
公开(公告)号：US07302669B1
公开(公告)日：2007-11-27
申请号：US11244648
申请日：2005-10-05
申请人： Peter Kazarian
发明人： Peter Kazarian
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Generating enable and data input signals for flip-flops used for implementing complex logic functions on a programmable logic device. The method includes ascertaining a behavioral logic equation that defines a logic function to be implemented on the programmable logic device, the logic function having one or more inputs and an output. A truth table is then derived from the behavioral logic equation. The truth table includes one or more minterms that collectively define all the possible states of the one or more inputs and the output of the logic function. Positive and negative cofactors of the logic function are defined from the minterms of the truth table. The defined positive and negative cofactors are used to ascertain an enable signal used to enable a flip-flop and logic circuitry to provide to a data input of the flip-flop. Together, the logic circuitry and the enable signal control the operation of the flip-flop to implement the logic function on the programmable logic device. In one embodiment, the aforementioned method is implemented in the programming software used for programming a PLD and maintained on a computer readable medium.
摘要翻译：生成用于在可编程逻辑器件上实现复杂逻辑功能的触发器的使能和数据输入信号。该方法包括确定定义要在可编程逻辑器件上实现的逻辑功能的行为逻辑方程，该逻辑功能具有一个或多个输入和输出。然后从行为逻辑方程派生真值表。真值表包括一个或多个minterms，它们共同定义了一个或多个输入的所有可能状态和逻辑功能的输出。逻辑函数的正和负辅助因子由真值表的最小值定义。定义的正和负辅助因子用于确定用于使触发器和逻辑电路能够提供给触发器的数据输入的使能信号。一起，逻辑电路和使能信号控制触发器的操作以在可编程逻辑器件上实现逻辑功能。在一个实施例中，上述方法在用于编程PLD并保存在计算机可读介质上的编程软件中实现。

5. 发明授权

US07126858B1 Apparatus for emulating asynchronous clear in memory structure and method for implementing the same 有权
标题翻译：用于模拟异步清除存储器结构的装置及其实现方法
公开(公告)号：US07126858B1
公开(公告)日：2006-10-24
申请号：US11156083
申请日：2005-06-17
申请人： Jinyong Yuan , Peter Kazarian
发明人： Jinyong Yuan , Peter Kazarian
IPC分类号： G11C7/10
CPC分类号： G11C7/22
摘要： Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a memory structure that does not support asynchronous clear capability. The emulation includes defining the memory cell to have a registered read address input and a data output connected to an input of a multiplexer. The register connected to the read address input of the multiplexer does not include an asynchronous clear connection. The data transmitted from the memory cell to the multiplexer is output from the multiplexer when an asynchronous clear signal has not been asserted. However, the multiplexer is further connected to output either null data or a ground signal in lieu of the data transmitted from the memory cell when an asynchronous clear signal has been asserted.
摘要翻译：公开了用于在存储器单元的读地址寄存器和存储器单元的数据输出寄存器中的每一个上模拟异步清零的电路，使得可以在不支持异步清除能力的存储器结构中定义存储器单元。仿真包括定义存储器单元以具有注册的读取地址输入和连接到多路复用器的输入的数据输出。连接到多路复用器的读地址输入的寄存器不包括异步清除连接。当异步清除信号尚未被断言时，从存储器单元发送到多路复用器的数据被从复用器输出。然而，当异步清除信号被断言时，多路复用器进一步连接以输出空数据或接地信号来代替从存储器单元发送的数据。

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