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1. 发明授权

US09342432B2 Hardware performance-monitoring facility usage after context swaps 有权
标题翻译：情景交换后的硬件性能监控设备使用情况
公开(公告)号：US09342432B2
公开(公告)日：2016-05-17
申请号：US13313557
申请日：2011-12-07
申请人： Giles R. Frazier , Brian R. Mestan
发明人： Giles R. Frazier , Brian R. Mestan
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F2201/865
摘要： A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs and provides accurate performance monitoring information. When a hypervisor signals that a task is being resumed and the application privilege level has been entered, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state, a state due to execution of the operating system or hypervisor, or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects branch information in a current program execution trace.
摘要翻译：性能监控技术提供任务切换免疫操作，而不需要在任务切换发生时存储和检索性能监视状态，并提供准确的性能监视信息。当管理程序发出信号指示正在恢复任务并且已经输入了应用程序权限级别时，它提供指示，其启动延迟定时器。在发生下一任务切换的情况下，在没有经过预定时间段的情况下，可以将延迟定时器复位。在延迟定时器到期后，恢复对性能监视器测量的分析，这阻止了初始状态，由于执行操作系统或管理程序的状态，或者从前一任务中剩余的状态破坏性能监视结果。性能监视器可以是或包括在当前程序执行跟踪中收集分支信息的执行跟踪单元。

2. 发明申请

US20120005462A1 Hardware Assist for Optimizing Code During Processing 审中-公开
标题翻译：处理过程中优化代码的硬件辅助
公开(公告)号：US20120005462A1
公开(公告)日：2012-01-05
申请号：US12828697
申请日：2010-07-01
申请人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
发明人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F9/3808 , G06F9/3844 , G06F11/348 , G06F2201/88
摘要： A method, data processing system, and computer program product for obtaining information about instructions. Instructions are processed. In response to processing a branch instruction in the instructions, a determination is made as to whether a result from processing the branch instruction follows a prediction of whether a branch is predicted to occur for the branch instruction. In response to the result following the prediction, the branch instruction is added to a current segment in a trace. In response to an absence of the result following the prediction, the branch instruction is added to the current segment in the trace and a first new segment and a second new segment are created. The first new segment includes a first branch instruction reached in the instructions from following the prediction. The second new segment includes a second branch instruction in the instructions reached from not following the prediction.
摘要翻译：一种用于获取关于指令的信息的方法，数据处理系统和计算机程序产品。处理说明。响应于在指令中处理分支指令，确定来自处理分支指令的结果是否遵循预测分支指令是否为分支指令发生的预测。响应于预测结果，分支指令被添加到跟踪中的当前段。响应于预测之后没有结果，分支指令被添加到跟踪中的当前段，并且创建第一新段和第二新段。第一个新的段包括在跟随预测的指令中达到的第一个分支指令。第二个新的段包括从不遵循预测到达的指令中的第二个分支指令。

3. 发明申请

US20100262813A1 Detecting and Handling Short Forward Branch Conversion Candidates 审中-公开
标题翻译：检测和处理短期分支转换候选人
公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译：在处理器中提供用于检测和处理短前进分支转换候选的机制。机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。

4. 发明申请

US20130055033A1 HARDWARE-ASSISTED PROGRAM TRACE COLLECTION WITH SELECTABLE CALL-SIGNATURE CAPTURE 审中-公开
标题翻译：硬件辅助程序跟踪采集与可选择的呼叫签名捕获
公开(公告)号：US20130055033A1
公开(公告)日：2013-02-28
申请号：US13300863
申请日：2011-11-21
申请人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
发明人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F11/3636 , G06F2201/83 , G06F2201/865
摘要： Hardware-assisted program tracing is facilitated by a processor that includes a root instruction address register, a program trace signature computation unit and a call signature register. When a program instruction having an address matching the root instruction address register is executed, a program trace signature is captured in the call signature register and capture of branch history is commenced. By accumulating different values of the call signature register, for example in response to an interrupt generated when the root instruction is executed, software that performs program tracing can obtain signatures of all of the multiple execution paths that lead to the root instruction, which is also specified by software in order to set different root instructions for program tracing. In an alternative implementation, a storage for multiple call signatures is provided in the processor and read at once by the software.
摘要翻译：硬件辅助程序跟踪由包括根指令地址寄存器，程序跟踪签名计算单元和呼叫签名寄存器的处理器来促进。当执行具有与根指令地址寄存器匹配的地址的程序指令时，在呼叫签名寄存器中捕获程序跟踪签名，并且开始分支历史记录的捕获。通过累积呼叫签名寄存器的不同值，例如响应于执行根指令时产生的中断，执行程序跟踪的软件可以获得导致根指令的所有多个执行路径的签名，这也是由软件指定，以便为程序跟踪设置不同的根指令。在替代实现中，在处理器中提供用于多个呼叫签名的存储器，并由软件一次读取。

5. 发明申请

US20120159125A1 EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH 有权
标题翻译：短环指导效率的效率
公开(公告)号：US20120159125A1
公开(公告)日：2012-06-21
申请号：US13408739
申请日：2012-02-29
申请人： Ronald D. Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald D. Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

6. 发明申请

US20120005463A1 BRANCH TRACE HISTORY COMPRESSION 失效
标题翻译：分行追踪历史压缩
公开(公告)号：US20120005463A1
公开(公告)日：2012-01-05
申请号：US12827916
申请日：2010-06-30
申请人： Brian R. Mestan , Mauricio J. Serrano
发明人： Brian R. Mestan , Mauricio J. Serrano
IPC分类号： G06F9/38
CPC分类号： G06F11/3476 , G06F2201/88
摘要： The disclosure provides a method, data processing system, and computer program product for managing a branch trace environment. In response to a branch being taken for a first branch instruction that is conditional and direct in the branch instructions, a performance monitoring unit stores an effective address of the first branch instruction into a first entry in a set of entries in a memory. The performance monitoring unit counts each branch not taken in processing the branch instructions occurring after the first branch instruction to form a branch count. In response to a branch being taken during processing of subsequent branch instructions in the branch instructions after the first branch instruction, the performance monitoring unit determines whether to create a second entry in the set of entries in the memory using the branch count with a set of rules identifying when the second entry is to be made.
摘要翻译：本公开提供了一种用于管理分支跟踪环境的方法，数据处理系统和计算机程序产品。响应于在分支指令中为有条件且直接的第一分支指令而分支，性能监视单元将第一分支指令的有效地址存储在存储器中的一组条目中的第一条目中。性能监视单元计算在处理在第一分支指令之后发生的分支指令时不采取的每个分支以形成分支计数。响应于在第一分支指令之后在分支指令中处理后续分支指令期间所采取的分支，性能监视单元使用具有一组分支计数的分支计数来确定是否在存储器中的条目集合中创建第二条目识别何时进行第二个条目的规则。

7. 发明申请

US20090113191A1 Apparatus and Method for Improving Efficiency of Short Loop Instruction Fetch 有权
标题翻译：提高短循环指令获取效率的装置和方法
公开(公告)号：US20090113191A1
公开(公告)日：2009-04-30
申请号：US11923709
申请日：2007-10-25
申请人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

8. 发明申请

US20120254837A1 TASK SWITCH IMMUNIZED PERFORMANCE MONITORING 有权
标题翻译：任务切换免疫性能监控
公开(公告)号：US20120254837A1
公开(公告)日：2012-10-04
申请号：US13079189
申请日：2011-04-04
申请人： GILES R. FRAZIER , David S. Levitan , Brian R. Mestan
发明人： GILES R. FRAZIER , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F2201/865
摘要： A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs. When a hypervisor signals that a task is being resumed, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects taken branches in a current trace and may use branch prediction success to determine whether to collect a predicted and taken branch instruction in a current trace or to start a new segment when the branch resolves in a non-predicted direction.
摘要翻译：性能监控技术提供任务切换免疫操作，而不需要在发生任务切换时存储和检索性能监视器状态。当管理程序发出任务正在恢复的信号时，它提供指示，启动一个延迟定时器。在发生下一任务切换的情况下，在没有经过预定时间段的情况下，可以将延迟定时器复位。在延迟定时器到期后，恢复对性能监视器测量的分析，这阻止了先前任务的初始状态或状态损坏性能监视结果。性能监视器可以是或包括执行跟踪单元，其在当前跟踪中收集所采取的分支，并且可以使用分支预测成功来确定是否在当前跟踪中收集预测和采取的分支指令，或者当分支解析时启动新分段处于非预测方向。

9. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

10. 发明申请

US20090113192A1 DESIGN STRUCTURE FOR IMPROVING EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH 有权
标题翻译：提高短路指令效率的设计结构
公开(公告)号：US20090113192A1
公开(公告)日：2009-04-30
申请号：US12132517
申请日：2008-06-03
申请人： RONALD HALL , Michael L. Karm , Brian R. Mestan , David Mui
发明人： RONALD HALL , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/3814 , G06F9/3851
摘要： A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：设计结构提供了处理器指令单元内的指令获取，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器的指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

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