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1. 发明申请

US20090113191A1 Apparatus and Method for Improving Efficiency of Short Loop Instruction Fetch 有权
标题翻译：提高短循环指令获取效率的装置和方法
公开(公告)号：US20090113191A1
公开(公告)日：2009-04-30
申请号：US11923709
申请日：2007-10-25
申请人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

2. 发明申请

US20090113192A1 DESIGN STRUCTURE FOR IMPROVING EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH 有权
标题翻译：提高短路指令效率的设计结构
公开(公告)号：US20090113192A1
公开(公告)日：2009-04-30
申请号：US12132517
申请日：2008-06-03
申请人： RONALD HALL , Michael L. Karm , Brian R. Mestan , David Mui
发明人： RONALD HALL , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/3814 , G06F9/3851
摘要： A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：设计结构提供了处理器指令单元内的指令获取，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器的指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

3. 发明授权

US09772851B2 Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer 有权
公开(公告)号：US09772851B2
公开(公告)日：2017-09-26
申请号：US11923709
申请日：2007-10-25
申请人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/40 , G06F1/32 , G06F9/38 , G06F9/32 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

4. 发明授权

US09395995B2 Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer 有权
标题翻译：检索单个分支的指令，从虚拟循环缓冲区向后循环
公开(公告)号：US09395995B2
公开(公告)日：2016-07-19
申请号：US13408739
申请日：2012-02-29
申请人： Ronald Hall , Michael L Karm , Brian R Mestan , David Mui
发明人： Ronald Hall , Michael L Karm , Brian R Mestan , David Mui
IPC分类号： G06F9/40 , G06F1/32 , G06F9/38 , G06F9/32
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system, and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.
摘要翻译：一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。处理器的指令单元中的指令取出在单个分支，向后的短循环的循环周期内，而不是从指令高速缓存中，从修改的缓冲器中检索短循环的指令。

5. 发明授权

US09052910B2 Efficiency of short loop instruction fetch 有权
标题翻译：短循环指令获取的效率
公开(公告)号：US09052910B2
公开(公告)日：2015-06-09
申请号：US12132517
申请日：2008-06-03
申请人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/3814 , G06F9/3851
摘要： A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：设计结构提供了处理器指令单元内的指令获取，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

6. 发明申请

US20120159125A1 EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH 有权
标题翻译：短环指导效率的效率
公开(公告)号：US20120159125A1
公开(公告)日：2012-06-21
申请号：US13408739
申请日：2012-02-29
申请人： Ronald D. Hall , Michael L. Karm , Brian R. Mestan , David Mui
发明人： Ronald D. Hall , Michael L. Karm , Brian R. Mestan , David Mui
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3802 , G06F1/3234 , G06F9/30189 , G06F9/30196 , G06F9/325 , G06F9/381 , G06F9/3814 , G06F9/3836 , G06F9/3851 , G06F12/0875 , G06F2212/452
摘要： A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache.
摘要翻译：一种用于在处理器指令单元内指令取出的方法，系统和计算机程序产品，利用循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。在指令获取期间，耦合到指令高速缓存（I-cache）的修改的指令缓冲器临时存储来自单个分支，向后短循环的指令。修改的指令缓冲器可以是循环缓冲器，一个或多个虚拟循环缓冲器和/或指令缓冲器。指令在循环周期长度存储在修改后的指令缓冲区中。处理器指令单元内的指令取出在循环周期内从修改的缓冲器而不是从指令高速缓存中检索短循环的指令。

7. 发明申请

US20090063819A1 Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US20090063819A1
公开(公告)日：2009-03-05
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

8. 发明授权

US09069563B2 Reducing store-hit-loads in an out-of-order processor 有权
标题翻译：减少无序处理器中的存储命中负载
公开(公告)号：US09069563B2
公开(公告)日：2015-06-30
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

9. 发明申请

US20130073833A1 REDUCING STORE-HIT-LOADS IN AN OUT-OF-ORDER PROCESSOR 有权
标题翻译：减少订单处理器中的存储负载
公开(公告)号：US20130073833A1
公开(公告)日：2013-03-21
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

10. 发明授权

US07779232B2 Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US07779232B2
公开(公告)日：2010-08-17
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/42 , G06F9/312
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

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