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1. 发明授权

US6094735A Speed-signaling testing for integrated circuits 有权
标题翻译：集成电路的速度信号测试
公开(公告)号：US6094735A
公开(公告)日：2000-07-25
申请号：US128041
申请日：1998-08-03
申请人： Clifford B. Cole , Joseph D. Coyne , Bijit T. Patel , Michael Shinkarovsky
发明人： Clifford B. Cole , Joseph D. Coyne , Bijit T. Patel , Michael Shinkarovsky
IPC分类号： G06F11/22 , G01R31/28 , G01R31/30 , G01R31/317
CPC分类号： G01R31/3016
摘要： An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.
摘要翻译：集成电路具有数字逻辑，其支持两种或多种不同的处理速度和两种或更多种不同的数据速率，每种数据速率由具有不同共模电压的数据前缀的每个数据速率区分。对于正常处理，集成电路具有一个或多个比较器，其将平均信号电压电平与一个或多个参考电压进行比较以确定数据速率。根据本发明的一个实施例，在比较器和数字逻辑之间配置一个或多个多路复用器。在测试期间可以控制这些多路复用器，以便旁路比较器的操作，以将指定的数字代码传递给数字逻辑以模拟比较器的操作。以这种方式，可以测试数字逻辑的不同处理速度，而无需构建特殊的自动测试设备来支持与不同支持的数据速率对应的所有不同的可能电压电平。

2. 发明授权

US5289580A Programmable multiple I/O interface controller 失效
标题翻译：可编程多个I / O接口控制器
公开(公告)号：US5289580A
公开(公告)日：1994-02-22
申请号：US698585
申请日：1991-05-10
申请人： Farrukh A. Latif , Michael D. Stevens , John A. Moysey , Michael Shinkarovsky , Hung Nguyen , Michele Z. Dale
发明人： Farrukh A. Latif , Michael D. Stevens , John A. Moysey , Michael Shinkarovsky , Hung Nguyen , Michele Z. Dale
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/385
摘要： An I/O interface controller is disclosed which can be programmed to interact with a variety of interface protocols. The host side and the peripheral side of the interface controller are independently programmable. All significant operations are performed in a single chip gate array. The gate array includes registers for establishing control with peripheral devices and for transferring data between peripheral devices and the host. An arithmetic logic unit is used for calculation and data manipulation while an I/O operation is occurring. A condition code multiplexer evaluates the contents of registers within the single chip and instructs the sequencer to perform various operations based on these results. Strobe signals from a peripheral device, indicating that valid data is ready to be transferred, are quickly acknowledged by virtue of an asynchronous signal path. The strobe signal is also processed so that it may correspond with the internal clock of the I/O interface. An asynchronous event driver and recognizer mechanism is also disclosed. This mechanism enable the I/O interface controller to drive the host side and the peripheral side interfaces simultaneously.
摘要翻译：公开了一种可被编程为与各种接口协议交互的I / O接口控制器。接口控制器的主机端和外围侧是独立可编程的。所有显着的操作都在单芯片门阵列中执行。门阵列包括用于与外围设备建立控制并用于在外围设备和主机之间传送数据的寄存器。在进行I / O操作时，使用算术逻辑单元进行计算和数据处理。条件代码复用器评估单个芯片内的寄存器的内容，并指示定序器根据这些结果执行各种操作。通过异步信号路径快速确认来自外围设备的指示有效数据准备传输的选通信号。选通信号也被处理，使其可以对应于I / O接口的内部时钟。还公开了异步事件驱动器和识别器机构。该机制使I / O接口控制器能够同时驱动主机端和外设端口。

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