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1. 发明授权

US07593411B2 Bus interface for transfer of multiple SONET/SDH rates over a serial backplane 失效
公开(公告)号：US07593411B2
公开(公告)日：2009-09-22
申请号：US11522381
申请日：2006-09-18
申请人： Carl D. McCrosky , Bernard Guay , Doug Konkin , Steven F. Lang , Winston K. Mok
发明人： Carl D. McCrosky , Bernard Guay , Doug Konkin , Steven F. Lang , Winston K. Mok
IPC分类号： H04L12/28
CPC分类号： H04J3/1611 , H04J3/14 , H04J2203/0062 , H04J2203/0089
摘要： A bus interface for transfer of SONET/SDH data that supports a plurality of SONET/SDH flows. The invention supports two line coding schemes: 8B/10B encoding of STS-12, and SONET scrambled coding for STS-12, STS-48, and STS-51. The invention additionally supports two modes of line testing: entire links can be tested by inserting and checking PRBS sequences, and the SPE payload of the largest concatenated STS-Nc which the link can carry (STS-12c, STS-48c, STS-51c) can be individually tested by inserting and checking PRBS sequences.

2. 发明授权

US5945860A CLM/ECL clock phase shifter with CMOS digital control 失效
标题翻译：具有CMOS数字控制的CLM / ECL时钟移相器
公开(公告)号：US5945860A
公开(公告)日：1999-08-31
申请号：US583169
申请日：1996-01-04
申请人： Bernard Guay , Michael Altmann
发明人： Bernard Guay , Michael Altmann
IPC分类号： H03C1/54 , H03K5/151 , H03K5/13 , H03K3/00
CPC分类号： H03C1/542 , H03K5/151
摘要： A CML/ECL clock phase shifter device provides a 360.degree. phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMOS current switch which generates current signals having the amplitude adjustable with the control signal, which is a digital word. Differential pairs provide amplitude modulated current signals for the input clock and the variant of the input clock. Two MOS transmission networks selectively invert each amplitude modulated signal and sum the signals from each side on a load network. The phase control resolution is optimal over four quadrants for quadrature input clock signals.
摘要翻译： CML / ECL时钟移相器装置提供360°相位控制范围，并且在被提供有与已知相位差相关的两个CML时钟信号时，该装置响应于控制信号产生任何期望的相位。该器件使用CMOS电流开关，其产生具有作为数字字的控制信号可调幅度的电流信号。差分对为输入时钟和输入时钟的变体提供幅度调制电流信号。两个MOS传输网络选择性地反转每个幅度调制信号，并且在负载网络上对来自每一侧的信号求和。正交输入时钟信号的四个象限的相位控制分辨率是最佳的。

3. 发明授权

US5825825A Method of processing multi-level signals for simple clock recovery 失效
标题翻译：处理多电平信号的简单时钟恢复方法
公开(公告)号：US5825825A
公开(公告)日：1998-10-20
申请号：US715218
申请日：1996-09-17
申请人： Michael Altmann , Bernard Guay
发明人： Michael Altmann , Bernard Guay
IPC分类号： H03K5/1532 , H04L7/033 , H04L25/49
CPC分类号： H03K5/1532 , H04L7/007 , H04L7/0331
摘要： A method and a circuit for simple clock recovery from multi-level at high transmission rates. The circuit is compatible with standard PLL-type clock recovery techniques for NRZ and generalized two-level signalling. The timing information is extracted from a single threshold crossing, irrespective of the number of levels (M) of the signal. This was verified to provide sufficient spectral information for the proper operation of a clock recovery PLL. The threshold may be programmed for various line codes.
摘要翻译：一种用于以高传输速率从多级简单时钟恢复的方法和电路。该电路与NRZ的标准PLL类型时钟恢复技术和广义的两级信号兼容。不考虑信号的电平（M）的数量，从单个阈值交叉提取定时信息。这被验证为提供足够的频谱信息用于时钟恢复PLL的正确操作。阈值可以针对各种线路代码进行编程。

4. 发明授权

US07543193B2 Serial data validity monitor 失效
标题翻译：串行数据有效性监视器
公开(公告)号：US07543193B2
公开(公告)日：2009-06-02
申请号：US10860548
申请日：2004-06-02
申请人： Ian Gordon Barrett , Gregory J. Erker , Michael James Smith , Scott Arthur Muma , Jeffrey S. Roe , Bernard Guay
发明人： Ian Gordon Barrett , Gregory J. Erker , Michael James Smith , Scott Arthur Muma , Jeffrey S. Roe , Bernard Guay
IPC分类号： G06F11/00
CPC分类号： H04L1/0061 , H04J3/0608 , Y10S370/907
摘要： A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance monitor is configured to detect DC imbalances in the incoming data and that may be indicative of errors in the data. The transition density detector is configured to detect whether a minimum transition density exists during a given time period. If a violation is detected by any one of these three detectors, an out-of-frame signal is asserted. The incoming data stream may be a scrambled SONET or SDH data stream.
摘要翻译：数据检测系统部分地包括CID检测器，DC平衡监视器和转换密度检测器。 CID检测器被配置为检测所接收的数据流是否包括超过预定阈值计数的CID。 DC平衡监视器被配置为检测输入数据中的直流不平衡，并且可以指示数据中的错误。转移密度检测器被配置为检测在给定时间段内是否存在最小转移密度。如果这三个检测器中的任一个检测到违规，则断言失帧信号。输入数据流可以是加扰的SONET或SDH数据流。

5. 发明申请

US20070036173A1 Bus interface for transfer of multiple SONET/SDH rates over a serial backplane 失效
标题翻译：总线接口，用于通过串行背板传输多个SONET / SDH速率
公开(公告)号：US20070036173A1
公开(公告)日：2007-02-15
申请号：US11522381
申请日：2006-09-18
申请人： Carl McCrosky , Bernard Guay , Doug Konkin , Steven Lang , Winston Mok
发明人： Carl McCrosky , Bernard Guay , Doug Konkin , Steven Lang , Winston Mok
IPC分类号： H04L12/66 , H04J3/06
CPC分类号： H04J3/1611 , H04J3/14 , H04J2203/0062 , H04J2203/0089
摘要： A bus interface for transfer of SONET/SDH data that supports a plurality of SONET/SDH flows. The invention supports two line coding schemes: 8B/10B encoding of STS-12, and SONET scrambled coding for STS-12, STS-48, and STS-51. The invention additionally supports two modes of line testing: entire links can be tested by inserting and checking PRBS sequences, and the SPE payload of the largest concatenated STS-Nc which the link can carry (STS-12c, STS-48c, STS-51c) can be individually tested by inserting and checking PRBS sequences.
摘要翻译：用于传送支持多个SONET / SDH流的SONET / SDH数据的总线接口。本发明支持两行编码方案：STS-12的8B / 10B编码，STS-12，STS-48和STS-51的SONET加扰编码。本发明另外支持两种线路测试模式：可以通过插入和检查PRBS序列以及链路可以携带的最大级联STS-Nc的SPE有效载荷来测试整个链路（STS-12c，STS-48c，STS-51c ）可以通过插入和检查PRBS序列来单独测试。

6. 发明授权

US4151278A Process for the preparation of an extract of Teucrium marum used in particular in therapy 失效
标题翻译：制备{i Teucrium marum {b特别用于治疗的提取物的制备方法
公开(公告)号：US4151278A
公开(公告)日：1979-04-24
申请号：US842364
申请日：1977-10-14
申请人： Jacques Debat , Jean Lemoine , Bernard Guay , Claude Crescioni
发明人： Jacques Debat , Jean Lemoine , Bernard Guay , Claude Crescioni
IPC分类号： A61K36/53 , A61K20060101 , A61K36/00 , A61P11/16 , C07G99/00 , A61K35/78 , C07G17/00
CPC分类号： A61K36/53
摘要： The present invention relates to a process for the preparation of an extract of Teucrium marum used in therapy, according to which the whole plant, or part of the plant, is subjected to a treatment with a solvent, the said process being characterized in that the said treatment is carried out with a solvent chosen from among the group comprising boiling water in the presence of NH.sub.3, pentane, hexane, heptane, cyclohexane, cyclopentane, petroleum ether, methylene chloride and mixtures of these, and in that, if necessary, the resulting extract is subjected to a purification.
摘要翻译：本发明涉及一种制备用于治疗的金枪鱼提取物的方法，根据该方法，将整个植物或植物的一部分用溶剂进行处理，所述方法的特征在于，在NH 3，戊烷，己烷，庚烷，环己烷，环戊烷，石油醚，二氯甲烷及其混合物的存在下，用选自沸水的溶剂进行处理，因此如果需要，使得到的提取物进行纯化。

7. 发明申请

US20050025195A1 Serial data validity monitor 失效
标题翻译：串行数据有效性监视器
公开(公告)号：US20050025195A1
公开(公告)日：2005-02-03
申请号：US10860548
申请日：2004-06-02
申请人： Ian Barrett , Gregory Erker , Michael Smith , Scott Muma , Jeffrey Roe , Bernard Guay
发明人： Ian Barrett , Gregory Erker , Michael Smith , Scott Muma , Jeffrey Roe , Bernard Guay
IPC分类号： H04J3/06 , H04L1/00 , H04J3/04
CPC分类号： H04L1/0061 , H04J3/0608 , Y10S370/907
摘要： A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance monitor is configured to detect DC imbalances in the incoming data and that may be indicative of errors in the data. The transition density detector is configured to detect whether a minimum transition density exists during a given time period. If a violation is detected by any one of these three detectors, an out-of-frame signal is asserted. The incoming data stream may be a scrambled SONET or SDH data stream.
摘要翻译：数据检测系统部分地包括CID检测器，DC平衡监视器和转换密度检测器。 CID检测器被配置为检测所接收的数据流是否包括超过预定阈值计数的CID。 DC平衡监视器被配置为检测输入数据中的直流不平衡，并且可以指示数据中的错误。转移密度检测器被配置为检测在给定时间段内是否存在最小转移密度。如果这三个检测器中的任一个检测到违规，则断言失帧信号。输入数据流可以是加扰的SONET或SDH数据流。

8. 发明授权

US5708391A High frequency differential filter with CMOS control 失效
标题翻译：具有CMOS控制的高频差分滤波器
公开(公告)号：US5708391A
公开(公告)日：1998-01-13
申请号：US643140
申请日：1996-05-02
申请人： Michael Altmann , Bernard Guay
发明人： Michael Altmann , Bernard Guay
IPC分类号： H03H11/12 , H03F3/45 , H03F3/191
CPC分类号： H03H11/1291 , H03H11/1213 , H03F2203/45504 , H03F2203/7203
摘要： A programmable high frequency active filter comprises a plurality of basic building blocks connected in parallel. A basic building block includes a transistor pair connected in a differential amplifier configuration, an impedance connected between the emitters of the transistors and a switching block for applying the necessary bias current to the transistors. The transfer function of the filter is programmed with a digital word, the length of which determines the number of basic building blocks included in the configuration. In this way, the equivalent high frequency impedance of the filter is controlled by selecting the configuration and the value of the impedance of each building block.
摘要翻译：可编程高频有源滤波器包括并联连接的多个基本构建块。基本构建块包括连接在差分放大器配置中的晶体管对，连接在晶体管的发射极之间的阻抗和用于将必要的偏置电流施加到晶体管的开关块。滤波器的传递函数用数字字编程，数字字的长度决定了配置中包含的基本构件的数量。以这种方式，通过选择每个结构单元的阻抗的配置和值来控制滤波器的等效高频阻抗。

9. 发明授权

US5420529A Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals 失效
标题翻译：电流转向开关和混合BiCMOS多路复用器，具有CMOS换向信号和CML / ECL数据信号
公开(公告)号：US5420529A
公开(公告)日：1995-05-30
申请号：US246207
申请日：1994-05-19
申请人： Bernard Guay , Michael Altmann
发明人： Bernard Guay , Michael Altmann
IPC分类号： H03K17/62 , H03K17/693 , H03K19/094
CPC分类号： H03K17/6292 , H03K17/693
摘要： A current steering switch circuit responsive to a CMOS signal. In an specific embodiment the switch is incorporated in a hybrid BiCMOS multiplexer circuit using combined CMOS and CML/ECL signal types. The high speed CML/ECL logic signals are multiplexed under the control of a lower speed CMOS signal. A particular aspect of the circuit is that a CMOS to CML/ECL converter is not used. Additionally, a differential, logic commutation signal is not required.
摘要翻译：响应于CMOS信号的电流转向开关电路。在具体实施例中，使用组合的CMOS和CML / ECL信号类型将开关并入混合BiCMOS多路复用器电路。高速CML / ECL逻辑信号在低速CMOS信号的控制下被复用。电路的一个特定方面是不使用CMOS到CML / ECL转换器。此外，不需要差分逻辑换向信号。

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