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1. 发明授权

US5285121A Current switching circuit 失效
标题翻译：电流开关电路
公开(公告)号：US5285121A
公开(公告)日：1994-02-08
申请号：US11184
申请日：1993-01-29
申请人： Mitsutoshi Sugawara
发明人： Mitsutoshi Sugawara
IPC分类号： G11B5/09 , H03K17/041 , H03K17/60 , H03K17/62 , H03F3/04 , H03F3/193
CPC分类号： H03K17/6292 , H03K17/04113
摘要： A current switching circuit includes a constant current source, a first transistor, a first resistor, second and third transistors, a selecting means, and a second resistor. The constant current source supplies a constant current. The first transistor is connected in series with the constant current source and has a base biased by one terminal of a power supply. The first resistor is connected between the first transistor and the other terminal of the power supply. The second and third transistors have collector currents as output currents and are rendered conductive by applying an output voltage of the first transistor to bases of the second and third transistors. The selecting means selectively applies the output voltage of the first transistor to the bases of the second and third transistors. The second resistor is connected between the other terminal of the power supply and a common connection point between emitters of the first and second transistors.
摘要翻译：电流切换电路包括恒流源，第一晶体管，第一电阻器，第二和第三晶体管，选择装置和第二电阻器。恒流源提供恒定电流。第一晶体管与恒流源串联连接，并具有由电源的一个端子偏置的基极。第一电阻器连接在第一晶体管和电源的另一端子之间。第二和第三晶体管具有集电极电流作为输出电流，并且通过将第一晶体管的输出电压施加到第二和第三晶体管的基极而导通。选择装置选择性地将第一晶体管的输出电压施加到第二和第三晶体管的基极。第二电阻器连接在电源的另一个端子和第一和第二晶体管的发射极之间的公共连接点。

2. 发明授权

US06002268A FPGA with conductors segmented by active repeaters 失效
标题翻译：具有由有源中继器分段的导体的FPGA
公开(公告)号：US06002268A
公开(公告)日：1999-12-14
申请号：US978691
申请日：1997-11-26
申请人： Paul Takao Sasaki , Madhukar Vora , Burnell G West
发明人： Paul Takao Sasaki , Madhukar Vora , Burnell G West
IPC分类号： H03K17/62 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1778 , H03K17/6257 , H03K17/6264 , H03K17/6285 , H03K17/6292 , H03K19/01759 , H03K19/1737 , H03K19/17704
摘要： An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU's simplifies software development for products within the family and as such contributes to faster "time to market".
摘要翻译：一种用于现场可编程门阵列的焊盘接口电路布局的接口电路，其具有多个I / O单元，每个I / O单元可被编程为输入或输出（或两者）和可编程连接矩阵，其提供可编程通道在由逻辑块的核心阵列和被编程为输出的I / O单元产生的数据输出信号之间，并且在被编程为输入的I / O单元和进入核心阵列的数据输入导体之间提供可编程通道。接口电路的结构基本相同，并且每个接口电路都包括足够数量的电源和接地连接，以向接口所具有的I / O单元的数量提供足够的电流。每个接口电路还包括至少一个并且优选两个开放空间，导电路径可布置在该开放空间中，以将功率传递到核心阵列，或将专用信号传送到也位于集成电路上的核心以外的电路。由于每个接口的结构基本相同，并且保持了I / O单元，电源和接地连接以及开放槽之间的比率，因此可以通过将附加的接口电路切割并粘贴到布局中来适应更大或更小的磁芯阵列，从而大大减少设计，放置和布局时间和上市时间，以便在具有较大核心阵列的家族中引入新的FPGA。 RIU的常规可重复结构简化了家庭产品的软件开发，因此有助于加快“上市时间”。

3. 发明授权

US3783307A Analog transmission gate 失效
标题翻译：模拟传输门
公开(公告)号：US3783307A
公开(公告)日：1974-01-01
申请号：US3783307D
申请日：1972-01-03
申请人： TRW INC
发明人： BREUER D
IPC分类号： H03F3/72 , H03K17/62 , H03K17/30 , H03K17/60
CPC分类号： H03K17/6264 , H03F3/72 , H03K17/6292
摘要： A transistor switching network, responding to a logic input, switches current selectively into one of a number of nodes, each node connecting a pair of bipolar transistors coupled differentially in a unity gain amplifier circuit. From a number of analog input signals applied to the differentially connected transistor pairs, only the one coupled to the selected node will produce an output from the voltage follower circuit. Conversely, a single analog input signal may be gated selectively to any one of a number of output terminals.
摘要翻译：晶体管开关网络响应于逻辑输入，选择性地将电流切换到多个节点之一，每个节点连接在单位增益放大器电路中差分耦合的一对双极晶体管。从施加到差分连接的晶体管对的多个模拟输入信号中，只有耦合到所选节点的模拟输入信号将产生来自电压跟随器电路的输出。相反，单个模拟输入信号可以选择性地选通到多个输出端子中的任何一个。

4. 发明公开

EP0307572A2 Multiple phase clock generator 失效
标题翻译： Mehrphasiger Taktgenerator。
公开(公告)号：EP0307572A2
公开(公告)日：1989-03-22
申请号：EP88111139.7
申请日：1988-07-12
申请人： TEKTRONIX, INC.
发明人： Traa, Einar Oddbjorn
IPC分类号： G06F1/04 , H03K5/15
CPC分类号： H03K5/15073 , H03K17/007 , H03K17/603 , H03K17/6292
摘要： A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.
摘要翻译：多相时钟发生器包括偶数个相位单元的环，每个相位单元产生单独的相位时钟信号。响应于来自环上的前一相位单元的使能信号和预偏置输出信号的同时断言，每相单元提供其相位时钟信号和预偏置输出信号。响应于主时钟信号中的状态变化，提供给环周围的每个相位单元的使能信号被断言并且被断言，允许同时提供提供给非相邻相位单元的信号。当使用一个相位单元来初始化其相位时钟信号和预偏置输出信号时，主时钟信号的每个转换使得环上的下一个相位单元提供其相位时钟输出信号。

5. 发明公开

EP0600475A2 A constant current switching circuit provided with a base current compensating circuit 失效
标题翻译：康斯坦丁·斯塔克斯克雷斯（Konstantstromschaltkreis）。
公开(公告)号：EP0600475A2
公开(公告)日：1994-06-08
申请号：EP93119388.2
申请日：1993-12-01
申请人： NEC CORPORATION
发明人： Narikawa, Hiroshi, c/o NEC IC Microcomputer , Tamura, Yoshiyuki, c/o NEC IC Microcomputer
IPC分类号： H03K17/62
CPC分类号： H03K17/6292
摘要： A current switching circuit has a setting section (2), a switching section (3) and a switch changeover section (4). The switching section (3) has a current mirror circuit, n switching transistors (TrSW1-TrSWn), and a compensating circuit. The current mirror circuit has first through third transistors (Tr1-Tr3). Emitters of the first and second transistors are connected to a power supply terminal (1) and bases thereof are connected with each other. The third transistor (Tr3) has an emitter connected to the bases of the first and second transistors (Tr1,Tr2), a collector grounded, and a base connected to a collector of the first transistor. The switching transistors (TrSW1-TrSWn) have emitters connected to the collector of the second transistor (Tr2), and collectors connected to one terminals of n load elements (Z1-Zn). The other terminals of the load elements are grounded. The switch changeover section (4) controls the base currents of the switching transistors (TrSW1-TrSWn). The compensating circuit comprises two compensating transistors (TrA,TrB). The first compensating transistor (TrA) has an emitter and a base connected to an emitter and a base of the second transistor (Tr2), respectively. The first compensating transistor (TrA) has a same size as that of the second transistor (Tr2). The second compensating transistor (TrB) has an emitter connected to a collector of the first compensating transistor (TrA), a collector grounded, and a base connected to the collector of the second transistor (Tr2). The second compensating transistor (TrB) has a same size as that of each of the n switching transistors (TrSW1-TrSWn).
摘要翻译：电流开关电路具有设定部（2），开关部（3）和开关切换部（4）。开关部分（3）具有电流镜电路，n个开关晶体管（TrSW1-TrSWn）和补偿电路。电流镜电路具有第一至第三晶体管（Tr1-Tr3）。第一和第二晶体管的发射极连接到电源端子（1），并且其基极彼此连接。第三晶体管（Tr3）具有连接到第一和第二晶体管（Tr1，Tr2）的基极的发射极，集电极接地，以及连接到第一晶体管的集电极的基极。开关晶体管（TrSW1-TrSWn）具有连接到第二晶体管（Tr2）的集电极的发射极，并且与n个负载元件（Z1-Zn）的一个端子连接的集电极。负载元件的其他端子接地。开关切换部分（4）控制开关晶体管（TrSW1-TrSWn）的基极电流。补偿电路包括两个补偿晶体管（TrA，TrB）。第一补偿晶体管（TrA）分别具有连接到第二晶体管（Tr2）的发射极和基极的发射极和基极。第一补偿晶体管（TrA）具有与第二晶体管（Tr2）相同的尺寸。第二补偿晶体管（TrB）具有连接到第一补偿晶体管（TrA）的集电极，集电极接地的发射极和连接到第二晶体管（Tr2）的集电极的基极）的发射极。第二补偿晶体管（TrB）具有与n个开关晶体管（TrSW1-TrSWn）中的每一个相同的尺寸。

6. 发明授权

EP0096944B1 Schaltungsanordnung mit mehreren, durch aktive Schaltungen gebildeten Signalpfaden 失效
标题翻译：具有主动安排形成的几个信号波形的电路
公开(公告)号：EP0096944B1
公开(公告)日：1985-12-04
申请号：EP83200872.6
申请日：1983-06-15
申请人： Philips Patentverwaltung GmbH , Philips Electronics N.V.
发明人： Graffenberger, Wilhelm , Kilian, Ernst-August , Dijkmans, Eise Carel
IPC分类号： H03F3/72 , H03K17/16
CPC分类号： H03K17/6292 , H03F1/305 , H03F3/72 , H03K17/16 , H03K17/602

7. 发明申请

WO99063666A1 MINIMAL HEADROOM, MINIMAL AREA MULTI-TERMINAL CURRENT STEERING CIRCUITS 审中-公开
标题翻译： MINIMAL HEADROOM，MINIMAL AREA多端电流转向电路
公开(公告)号：WO99063666A1
公开(公告)日：1999-12-09
申请号：PCT/US1999/012234
申请日：1999-06-02
IPC分类号： H03K17/00 , H03K17/041 , H03K17/62
CPC分类号： H03K17/04113 , H03K17/6292 , H03K2217/0036
摘要： Minimal headroom, minimal area, multi-terminal current steering circuits for steering a current from a current source (I1) to any one of a plurality of outputs. The steering circuit provides controls to individual steering transistors (Q1, Q2, Q3) so as to turn on the selected one of the plurality of steering transistors responsive to steering control signals. Minimal headroom is required, and beta dependent errors in the current output are minimized, by steering the current source through only a single transistor to the selected output. This also minimizes chip area. Alternate embodiments are disclosed and described.
摘要翻译：用于将来自电流源（I1）的电流转换为多个输出中的任何一个的多端子电流转向电路的最小余量，最小面积。转向电路为单独的转向晶体管（Q1，Q2，Q3）提供控制，以响应于转向控制信号来接通多个转向晶体管中选定的一个。需要最小的余量，通过将电流源通过仅一个晶体管转向所选输出，将电流输出中的β相关误差最小化。这也使芯片面积最小化。公开和描述了替代实施例。

8. 发明公开

EP0600475A3 A constant current switching circuit provided with a base current compensating circuit 失效
标题翻译：与基极电流补偿电路提供的恒流电路。
公开(公告)号：EP0600475A3
公开(公告)日：1995-01-25
申请号：EP93119388.2
申请日：1993-12-01
申请人： NEC CORPORATION
发明人： Narikawa, Hiroshi, c/o NEC IC Microcomputer , Tamura, Yoshiyuki, c/o NEC IC Microcomputer
IPC分类号： H03K17/62
CPC分类号： H03K17/6292
摘要： A current switching circuit has a setting section (2), a switching section (3) and a switch changeover section (4). The switching section (3) has a current mirror circuit, n switching transistors (TrSW1-TrSWn), and a compensating circuit. The current mirror circuit has first through third transistors (Tr1-Tr3). Emitters of the first and second transistors are connected to a power supply terminal (1) and bases thereof are connected with each other. The third transistor (Tr3) has an emitter connected to the bases of the first and second transistors (Tr1,Tr2), a collector grounded, and a base connected to a collector of the first transistor. The switching transistors (TrSW1-TrSWn) have emitters connected to the collector of the second transistor (Tr2), and collectors connected to one terminals of n load elements (Z1-Zn). The other terminals of the load elements are grounded. The switch changeover section (4) controls the base currents of the switching transistors (TrSW1-TrSWn). The compensating circuit comprises two compensating transistors (TrA,TrB). The first compensating transistor (TrA) has an emitter and a base connected to an emitter and a base of the second transistor (Tr2), respectively. The first compensating transistor (TrA) has a same size as that of the second transistor (Tr2). The second compensating transistor (TrB) has an emitter connected to a collector of the first compensating transistor (TrA), a collector grounded, and a base connected to the collector of the second transistor (Tr2). The second compensating transistor (TrB) has a same size as that of each of the n switching transistors (TrSW1-TrSWn).

9. 发明授权

EP0307572B1 Multiple phase clock generator 失效
标题翻译：多相时钟发生器
公开(公告)号：EP0307572B1
公开(公告)日：1993-09-29
申请号：EP88111139.7
申请日：1988-07-12
申请人： TEKTRONIX, INC.
发明人： Traa, Einar Oddbjorn
IPC分类号： G06F1/04 , H03K5/15
CPC分类号： H03K5/15073 , H03K17/007 , H03K17/603 , H03K17/6292

10. 发明授权

US5532631A Active pull-down write driver for three-terminal inductive load 失效
标题翻译：用于三端感性负载的主动下拉式写入驱动器
公开(公告)号：US5532631A
公开(公告)日：1996-07-02
申请号：US341495
申请日：1994-11-17
申请人： Tuan V. Ngo , Raymond E. Barnett
发明人： Tuan V. Ngo , Raymond E. Barnett
IPC分类号： H03K17/041 , H03K17/62 , H03K3/00 , H03K4/04
CPC分类号： H03K17/04113 , H03K17/6292
摘要： A write driver for a magnetic transducer having a three-terminal inductive coil includes first and second voltage sources, a write current source, and a switching network having first and second switching transistors connected between the second voltage source and the respective first and second taps. The switching network responds to respective first and second inputs to switch the write current between respective first and second taps. Active pull-down subcircuits operate to alternately supply base current to the respective first and second switching transistors to charge parasitic capacitances of the respective switching transistors and to alternately sink base current from the respective switching transistors to discharge parasitic capacitances.
摘要翻译：具有三端感应线圈的磁换能器的写驱动器包括第一和第二电压源，写电流源和具有连接在第二电压源与相应的第一和第二抽头之间的第一和第二开关晶体管的开关网络。交换网络响应相应的第一和第二输入以在相应的第一和第二抽头之间切换写入电流。有源下拉子电路用于交替地向相应的第一和第二开关晶体管提供基极电流，以对各个开关晶体管的寄生电容进行充电，并交替地从相应的开关晶体管吸收基极电流以放电寄生电容。

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