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1. 发明申请

US20130176154A1 OFF-LINE GAIN CALIBRATION IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：时间间隔模拟数字转换器的离线增益校准
公开(公告)号：US20130176154A1
公开(公告)日：2013-07-11
申请号：US13346242
申请日：2012-01-09
申请人： Anthony R. BONACCIO , Frank R. KEYSER, III , Martin L. SCHMATZ , Benjamin T. VOEGLI
发明人： Anthony R. BONACCIO , Frank R. KEYSER, III , Martin L. SCHMATZ , Benjamin T. VOEGLI
IPC分类号： H03M1/06 , H03M1/10
CPC分类号： H03M1/182 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.
摘要翻译：时间交织的模数转换器（ADC）包括多个ADC块，每个ADC块包括：至少一个ADC单元，被配置为将模拟输入转换成数字输出; 以及数字增益控制器，被配置为基于所述至少一个ADC单元的实际输出与所述至少一个ADC单元的预期输出的比较来调整所述至少一个ADC单元的参考电压。

2. 发明授权

US07966537B2 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US07966537B2
公开(公告)日：2011-06-21
申请号：US12479914
申请日：2009-06-08
申请人： Anthony R. Bonaccio , Michael LeStrange , William R. Tonti , Sebastian T. Ventrone
发明人： Anthony R. Bonaccio , Michael LeStrange , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G01R31/28
CPC分类号： G06F1/04
摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.
摘要翻译：一种用于防止集成电路故障的电路。电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路，从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

3. 发明授权

US07823002B2 Digital reliability monitor having autonomic repair and notification capability 有权
标题翻译：数字可靠性监控器具有自主修复和通知功能
公开(公告)号：US07823002B2
公开(公告)日：2010-10-26
申请号：US11772418
申请日：2007-07-02
申请人： Anthony R. Bonaccio , Michael LeStrange , William R. Tonti , Sebastian T. Ventrone
发明人： Anthony R. Bonaccio , Michael LeStrange , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G06F1/00 , G06F1/04 , G06F11/00
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译：一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

4. 发明授权

US07770139B2 Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path 失效
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构
公开(公告)号：US07770139B2
公开(公告)日：2010-08-03
申请号：US11931626
申请日：2007-10-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

5. 发明申请

US20090106707A1 Multiple Source-Single Drain Field Effect Semiconductor Device and Circuit 有权
标题翻译：多源单漏极场效应半导体器件与电路
公开(公告)号：US20090106707A1
公开(公告)日：2009-04-23
申请号：US11873515
申请日：2007-10-17
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的设计结构的实施例，其可被单独地和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

6. 发明授权

US07477541B2 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US07477541B2
公开(公告)日：2009-01-13
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

7. 发明申请

US20080186054A1 DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH 有权
标题翻译：用于可配置混合逻辑信号分配路径的灵活多模态逻辑单元的设计结构
公开(公告)号：US20080186054A1
公开(公告)日：2008-08-07
申请号：US11848470
申请日：2007-08-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译：公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。特别地，用于示例性多模电路的设计结构可以被配置为以全摆动模式，限定摆动模式，全摆幅至限定摆动转换器模式和限定摆动转换模式中的一种运行，摆动转换器模式。多模电路的工作模式可以动态地选择。一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。

8. 发明授权

US07403039B1 Flexible multimode logic element for use in a configurable mixed-logic signal distribution path 有权
公开(公告)号：US07403039B1
公开(公告)日：2008-07-22
申请号：US11670537
申请日：2007-02-02
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/018585 , H03K3/35613 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03K2005/00228
摘要： A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.

9. 发明申请

US20080143373A1 USING ELECTRICALLY PROGRAMMABLE FUSES TO HIDE ARCHITECTURE, PREVENT REVERSE ENGINEERING, AND MAKE A DEVICE INOPERABLE 失效
标题翻译：使用电子可编程熔丝来隐藏建筑物，防止反向工程，并使设备无效
公开(公告)号：US20080143373A1
公开(公告)日：2008-06-19
申请号：US12039829
申请日：2008-02-29
申请人： Anthony R. BONACCIO , Karl R. ERICKSON , John A. FIFIELD , Chandrasekharan KOTHANDARAMAN , Phil C. PAONE , William R. TONTI
发明人： Anthony R. BONACCIO , Karl R. ERICKSON , John A. FIFIELD , Chandrasekharan KOTHANDARAMAN , Phil C. PAONE , William R. TONTI
IPC分类号： H03K19/00
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

10. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

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