专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150031187A1 METHODS FOR FORMING A ROUND BOTTOM SILICON TRENCH RECESS FOR SEMICONDUCTOR APPLICATIONS 有权
标题翻译：用于形成用于半导体应用的圆形底部硅离子注入的方法
公开(公告)号：US20150031187A1
公开(公告)日：2015-01-29
申请号：US13948269
申请日：2013-07-23
申请人： Joo Won Han , Kee Young CHO , Han Sao CHO , Sang Wook KIM , Anisul H. KHAN
发明人： Joo Won Han , Kee Young CHO , Han Sao CHO , Sang Wook KIM , Anisul H. KHAN
IPC分类号： H01L21/762
CPC分类号： H01L21/3065 , H01J37/32082 , H01J2237/3347 , H01L21/30655 , H01L21/31116 , H01L21/67109 , H01L21/6831 , H01L21/76224 , H01L21/76898 , H01L29/66621
摘要： Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
摘要翻译：本发明的实施例提供了蚀刻半导体衬底（例如含硅材料）中的凹槽通道的方法。在一个实施例中，在半导体衬底中形成凹陷结构的方法包括将硅衬底转移到其中设置有图案化光致抗蚀剂层的处理室中，暴露一部分衬底，提供包含含卤素气体和 Cl 2气体进入处理室，提供RF源功率以从蚀刻气体混合物形成等离子体，在蚀刻气体混合物中提供脉冲RF偏置功率，以及蚀刻通过图案化光致抗蚀剂层暴露的硅衬底的部分，存在等离子体。

2. 发明申请

US20120088371A1 METHODS FOR ETCHING SUBSTRATES USING PULSED DC VOLTAGE 审中-公开
标题翻译：使用脉冲直流电压蚀刻基板的方法
公开(公告)号：US20120088371A1
公开(公告)日：2012-04-12
申请号：US13089374
申请日：2011-04-19
申请人： ALOK RANJAN , NICOLAS GANI , MEIHUA SHEN , ANISUL H. KHAN
发明人： ALOK RANJAN , NICOLAS GANI , MEIHUA SHEN , ANISUL H. KHAN
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01J37/32082 , H01J37/32697 , H01J2237/334 , H01L21/31116 , H01L21/32136
摘要： Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.
摘要翻译：本文提供了使用脉冲DC电压蚀刻基板的方法。在一些实施例中，用于蚀刻设置在处理室内的衬底支撑件上的衬底的方法的方法可包括向处理室提供工艺气体; 从工艺气体形成等离子体; 向设置在处理室内的第一电极施加脉冲DC电压; 并在施加脉冲DC电压的同时刻蚀衬底。

3. 发明授权

US08596336B2 Substrate support temperature control 有权
标题翻译：基板支持温度控制
公开(公告)号：US08596336B2
公开(公告)日：2013-12-03
申请号：US12132101
申请日：2008-06-03
申请人： Richard Fovell , Paul Brillhart , Sang In Yi , Anisul H. Khan , Jivko Dinev , Shane Nevil
发明人： Richard Fovell , Paul Brillhart , Sang In Yi , Anisul H. Khan , Jivko Dinev , Shane Nevil
IPC分类号： F22B37/00 , G05D9/00 , B05C11/00
CPC分类号： F28D15/00 , F28D2021/0077 , H01L21/67109 , H01L21/67248
摘要： Apparatus for controlling the temperature of a substrate support may include a first heat transfer loop and a second heat transfer loop. The first heat transfer loop may have a first bath with a first heat transfer fluid at a first temperature. The second heat transfer loop may have a second bath with a second heat transfer fluid at a second temperature. The first and second temperatures may be the same or different. First and second flow controllers may be provided for respectively providing the first and second heat transfer fluids to a substrate support. One or more return lines may couple one or more outlets of the substrate support to the first and second baths for returning the first and second heat transfer fluids to the first and second baths.
摘要翻译：用于控制衬底支撑件的温度的装置可以包括第一传热回路和第二传热回路。第一传热回路可以具有在第一温度下具有第一传热流体的第一浴。第二传热回路可以具有在第二温度下具有第二传热流体的第二浴。第一和第二温度可以相同或不同。可以提供第一和第二流量控制器以分别将第一和第二传热流体提供给基板支撑件。一个或多个返回线可以将衬底支撑件的一个或多个出口连接到第一和第二浴，以将第一和第二传热流体返回到第一和第二浴。

4. 发明申请

US20080286978A1 ETCHING AND PASSIVATING FOR HIGH ASPECT RATIO FEATURES 审中-公开
标题翻译：用于高比例特征的蚀刻和钝化
公开(公告)号：US20080286978A1
公开(公告)日：2008-11-20
申请号：US11749957
申请日：2007-05-17
申请人： Rong Chen , Tae Won Kim , Nicolas Gani , Anisul H. Khan
发明人： Rong Chen , Tae Won Kim , Nicolas Gani , Anisul H. Khan
IPC分类号： H01L21/302
CPC分类号： H01L21/30655
摘要： An etch method includes etching a masked substrate to form a recess with a first sidewall in the substrate. A thin surface layer of the substrate on the first sidewall is then converted into a passivation layer. The masked substrate is etched again to deepen the recess in the substrate. A surface layer of the substrate on the second sidewall of the recess is then converted into a passivation layer. In one embodiment, upon removal of the passivation layers from both sidewalls, the first and second sidewalls of the high aspect ratio recess are aligned to within 10 Å of each other to provide a high aspect ratio recess having a vertical profile.
摘要翻译：蚀刻方法包括蚀刻被掩蔽的衬底以在衬底中形成具有第一侧壁的凹部。然后将第一侧壁上的衬底的薄表面层转换成钝化层。再次蚀刻掩蔽的衬底以加深衬底中的凹部。然后将凹槽的第二侧壁上的衬底的表面层转换成钝化层。在一个实施例中，在从两个侧壁去除钝化层时，高纵横比凹槽的第一和第二侧壁彼此对准，以提供具有垂直剖面的高纵横比凹槽。

5. 发明授权

US08747684B2 Multi-film stack etching with polymer passivation of an overlying etched layer 失效
标题翻译：多层叠层蚀刻与上覆蚀刻层的聚合物钝化
公开(公告)号：US08747684B2
公开(公告)日：2014-06-10
申请号：US12860672
申请日：2010-08-20
申请人： Sunil Srinivasan , Jinhan Choi , Anisul H. Khan
发明人： Sunil Srinivasan , Jinhan Choi , Anisul H. Khan
IPC分类号： B44C1/22
CPC分类号： C23F4/00 , H01J37/32449 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/67069 , H01L27/0688
摘要： A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.
摘要翻译：一种用于等离子体蚀刻诸如半导体晶片的工件的方法和装置，包括具有设置在底部膜上的顶部薄膜的薄膜叠层，其间具有介于其间的中间膜。顶部和底部薄膜之间的蚀刻选择性可以低至1：1和2：1之间，并且使用第一种贫碳气体化学品来蚀刻顶部薄膜，第二种贫碳气体化学物质用于蚀刻通过使用富碳气体化学沉积顶部膜上的聚合物钝化物和用可能相同的第三种贫碳气体化学物质对底部膜进行蚀刻，交替地蚀刻中间膜和底部膜作为第一个贫碳气体化学。

6. 发明授权

US06905616B2 Method of releasing devices from a substrate 失效
标题翻译：从基板释放装置的方法
公开(公告)号：US06905616B2
公开(公告)日：2005-06-14
申请号：US10382562
申请日：2003-03-05
申请人： Ajay Kumar , Anisul H Khan , Sanjay M Thekdi , Sharma V Pamarthy
发明人： Ajay Kumar , Anisul H Khan , Sanjay M Thekdi , Sharma V Pamarthy
IPC分类号： B31D3/00 , B44C1/22 , B81C1/00 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/00
CPC分类号： B81C1/00952
摘要： Micro devices are formed in situ in a high density in a substrate comprising a masked silicon layer over a stop layer of a silicon compound, by anisotropically etching the desired feature in the silicon layer, overetching to form a notch at the silicon-stop layer interface, depositing a protective fluorocarbon polymer layer on the sidewalls and bottom of the etched silicon layer, and isotropically etching to separate the etched feature from the stop layer. This method avoids the problems of stiction common in other methods of forming micro devices.
摘要翻译：通过各向异性地蚀刻硅层中的所需特征，在基底上形成微孔器件，在衬底上形成掩模硅层，通过各向异性蚀刻硅层中的所需特征，过蚀刻以在硅 - 停止层界面处形成缺口，在蚀刻硅层的侧壁和底部上沉积保护性碳氟聚合物层，并进行各向同性蚀刻以将蚀刻的特征与停止层分离。这种方法避免了在其他形成微器件的方法中常见的静电问题。

7. 发明授权

US06759340B2 Method of etching a trench in a silicon-on-insulator (SOI) structure 失效
标题翻译：蚀刻绝缘体上硅（SOI）结构中的沟槽的方法
公开(公告)号：US06759340B2
公开(公告)日：2004-07-06
申请号：US10143269
申请日：2002-05-09
申请人： Padmapani C. Nallan , Ajay Kumar , Anisul H. Khan , Chan-Syun David Yang
发明人： Padmapani C. Nallan , Ajay Kumar , Anisul H. Khan , Chan-Syun David Yang
IPC分类号： H01L21302
CPC分类号： H01L21/30655
摘要： Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.
摘要翻译：本文公开了一种在覆盖电介质材料的硅中蚀刻沟槽的方法，其减小或基本上消除在沟槽的基部处的凹口，同时减少沟槽侧壁上的扇形。该方法包括通过将硅衬底通过图案化掩模层暴露于由含氟气体产生的等离子体来蚀刻沟槽的第一部分。该蚀刻之后是聚合物沉积步骤，包括将衬底暴露于由能够在蚀刻的硅表面上形成聚合物的气体产生的等离子体。根据沟槽第一部分的期望深度，蚀刻和聚合物沉积步骤重复多个循环。通过将硅暴露于由含氟气体和聚合物形成气体的组合产生的等离子体来蚀刻沟槽的最后部分。

8. 发明授权

US08932947B1 Methods for forming a round bottom silicon trench recess for semiconductor applications 有权
标题翻译：用于形成用于半导体应用的圆底硅沟槽凹槽的方法
公开(公告)号：US08932947B1
公开(公告)日：2015-01-13
申请号：US13948269
申请日：2013-07-23
申请人： Joo Won Han , Kee Young Cho , Han Soo Cho , Sang Wook Kim , Anisul H. Khan
发明人： Joo Won Han , Kee Young Cho , Han Soo Cho , Sang Wook Kim , Anisul H. Khan
IPC分类号： H01L21/302 , H01L21/762 , H01L21/768 , H01L21/311 , H01L21/3065
CPC分类号： H01L21/3065 , H01J37/32082 , H01J2237/3347 , H01L21/30655 , H01L21/31116 , H01L21/67109 , H01L21/6831 , H01L21/76224 , H01L21/76898 , H01L29/66621
摘要： Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
摘要翻译：本发明的实施例提供了蚀刻半导体衬底（例如含硅材料）中的凹槽通道的方法。在一个实施例中，在半导体衬底中形成凹陷结构的方法包括将硅衬底转移到其中设置有图案化光致抗蚀剂层的处理室中，暴露一部分衬底，提供包含含卤素气体和 Cl 2气体进入处理室，提供RF源功率以从蚀刻气体混合物形成等离子体，在蚀刻气体混合物中提供脉冲RF偏置功率，以及蚀刻通过图案化光致抗蚀剂层暴露的硅衬底的部分，存在等离子体。

9. 发明申请

US20110045672A1 MULTI-FILM STACK ETCHING WITH POLYMER PASSIVATION OF AN OVERLYING ETCHED LAYER 失效
标题翻译：多层蚀刻层的聚合物钝化的多层堆叠蚀刻
公开(公告)号：US20110045672A1
公开(公告)日：2011-02-24
申请号：US12860672
申请日：2010-08-20
申请人： Sunil Srinivasan , Jinhan Choi , Anisul H. Khan
发明人： Sunil Srinivasan , Jinhan Choi , Anisul H. Khan
IPC分类号： H01L21/3065 , C23F1/08
CPC分类号： C23F4/00 , H01J37/32449 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L21/67069 , H01L27/0688
摘要： A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.
摘要翻译：一种用于等离子体蚀刻诸如半导体晶片的工件的方法和装置，包括具有设置在底部膜上的顶部薄膜的薄膜叠层，其间具有介于其间的中间膜。顶部和底部薄膜之间的蚀刻选择性可以低至1：1和2：1之间，并且使用第一种贫碳气体化学品来蚀刻顶部薄膜，第二种贫碳气体化学物质用于蚀刻通过使用富碳气体化学沉积顶部膜上的聚合物钝化物和用可能相同的第三种贫碳气体化学物质对底部膜进行蚀刻，交替地蚀刻中间膜和底部膜作为第一个贫碳气体化学。

10. 发明申请

US20090294101A1 FAST SUBSTRATE SUPPORT TEMPERATURE CONTROL 有权
标题翻译：快速基板支持温度控制
公开(公告)号：US20090294101A1
公开(公告)日：2009-12-03
申请号：US12132101
申请日：2008-06-03
申请人： RICHARD FOVELL , Paul Brillhart , Sang In Yi , Anisul H. Khan , Jivko Dinev , Shane Nevil
发明人： RICHARD FOVELL , Paul Brillhart , Sang In Yi , Anisul H. Khan , Jivko Dinev , Shane Nevil
IPC分类号： F28D15/00
CPC分类号： F28D15/00 , F28D2021/0077 , H01L21/67109 , H01L21/67248
摘要： Methods and apparatus for controlling the temperature of a substrate support are provided herein. In some embodiments, an apparatus for controlling the temperature of a substrate support may include a first heat transfer loop and a second heat transfer loop. The first heat transfer loop may have a first bath with a first heat transfer fluid at a first temperature. The second heat transfer loop may have a second bath with a second heat transfer fluid at a second temperature. The first and second temperatures may be the same or different. First and second flow controllers may be provided for respectively providing the first and second heat transfer fluids to a substrate support. One or more return lines may couple one or more outlets of the substrate support to the first and second baths for returning the first and second heat transfer fluids to the first and second baths.
摘要翻译：本文提供了用于控制基板支撑件的温度的方法和装置。在一些实施例中，用于控制衬底支撑件的温度的装置可以包括第一传热回路和第二传热回路。第一传热回路可以具有在第一温度下具有第一传热流体的第一浴。第二传热回路可以具有在第二温度下具有第二传热流体的第二浴。第一和第二温度可以相同或不同。可以提供第一和第二流量控制器以分别将第一和第二传热流体提供给基板支撑件。一个或多个返回线可以将衬底支撑件的一个或多个出口连接到第一和第二浴，以将第一和第二传热流体返回到第一和第二浴。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式