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1. 发明申请

US20120049940A1 VERTICAL-CONDUCTION INTEGRATED ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THEREOF 有权
标题翻译：垂直导体集成电子器件及其制造方法
公开(公告)号：US20120049940A1
公开(公告)日：2012-03-01
申请号：US13221694
申请日：2011-08-30
申请人： Ferruccio FRISINA , Mario Giuseppe SAGGIO , Angelo MAGRI'
发明人： Ferruccio FRISINA , Mario Giuseppe SAGGIO , Angelo MAGRI'
IPC分类号： G05F3/02 , H01L29/24 , H01L29/73 , H01L21/20 , H01L29/02 , H01L29/78
CPC分类号： H01L29/7806 , H01L21/02573 , H01L21/046 , H01L21/265 , H01L29/0619 , H01L29/0821 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/66068 , H01L29/732 , H01L29/7371 , H01L29/7802 , H01L29/7804 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.
摘要翻译：形成在半导体材料体内的垂直导电集成电子器件的实施例包括：由第一半导体材料制成并具有第一导电类型的衬底，第一半导体材料具有第一带隙; 由第一半导体材料制成并且具有第一类型的导电性的外延区域，其覆盖在衬底上并限定第一表面; 以及由第二半导体材料制成的第一外延层，其覆盖在第一表面上并与外延区直接接触，第二半导体材料具有比第一带隙窄的第二带隙。身体还包括延伸在第一表面下方和外延区域内的第二类导电性的深区域。

2. 发明申请

US20120056200A1 INTEGRATED ELECTRONIC DEVICE WITH EDGE-TERMINATION STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有边缘结构的集成电子设备及其制造方法
公开(公告)号：US20120056200A1
公开(公告)日：2012-03-08
申请号：US13221778
申请日：2011-08-30
申请人： Ferruccio FRISINA , Angelo MAGRI' , Mario Giuseppe SAGGIO
发明人： Ferruccio FRISINA , Angelo MAGRI' , Mario Giuseppe SAGGIO
IPC分类号： H01L29/16 , H01L21/20 , H01L21/02 , H01L29/06
CPC分类号： H01L29/66666 , H01L21/02529 , H01L21/02532 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/66431 , H01L29/7811 , H01L29/7813
摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
摘要翻译：一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

3. 发明申请

US20100163888A1 MANUFACTURING PROCESS OF A POWER ELECTRONIC DEVICE INTEGRATED IN A SEMICONDUCTOR SUBSTRATE WITH WIDE BAND GAP AND ELECTRONIC DEVICE THUS OBTAINED 有权
标题翻译：集成在具有宽带隙的半导体衬底和获得的电子器件的功率电子器件的制造过程
公开(公告)号：US20100163888A1
公开(公告)日：2010-07-01
申请号：US12641146
申请日：2009-12-17
申请人： Mario Giuseppe SAGGIO , Edoardo ZANETTI , Ferruccio FRISINA
发明人： Mario Giuseppe SAGGIO , Edoardo ZANETTI , Ferruccio FRISINA
IPC分类号： H01L29/24 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7811 , H01L21/0485 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/1608 , H01L29/402 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/66666 , H01L29/7802
摘要： An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type. The process comprises the steps of: forming, on the semiconductor body, a first mask having a first window and a second window above a first surface portion and a second surface portion of the semiconductor body; forming, within the first and second surface portions of the semiconductor body underneath the first and second windows, at least one first conductive region and one second conductive region having a second conductivity type, the first conductive region and the second conductive region facing one another; forming a second mask on the semiconductor body, the second mask having a plurality of windows above surface portions of the first conductive region and the second conductive region; forming, within the first conductive region and the second conductive region and underneath the plurality of windows, a plurality of third conductive regions having the first conductivity type; removing completely the first and second masks; performing an activation thermal process of the first, second, and third conductive regions at a high temperature; and forming body and source regions.
摘要翻译：一种用于制造具有第一导电类型的具有宽禁带隙的材料的半导体本体上的电子器件的方法的实施例。该方法包括以下步骤：在半导体本体上形成第一掩模，该第一掩模在半导体本体的第一表面部分和第二表面部分之上具有第一窗口和第二窗口; 在第一和第二窗口下面的半导体本体的第一和第二表面部分内形成具有第二导电类型的至少一个第一导电区域和一个第二导电区域，第一导电区域和第二导电区域彼此面对; 在所述半导体主体上形成第二掩模，所述第二掩模在所述第一导电区域和所述第二导电区域的表面部分上方具有多个窗口; 在所述第一导电区域和所述第二导电区域内以及所述多个窗口下方形成具有所述第一导电类型的多个第三导电区域; 彻底清除第一和第二掩模; 在高温下进行第一，第二和第三导电区域的激活热处理; 并形成体和源区。

4. 发明申请

US20060186434A1 VERTICAL-CONDUCTION AND PLANAR-STRUCTURE MOS DEVICE WITH A DOUBLE THICKNESS OF GATE OXIDE AND METHOD FOR REALIZING POWER VERTICAL MOS TRANSISTORS WITH IMPROVED STATIC AND DYNAMIC PERFORMANCE AND HIGH SCALING DOWN DENSITY 有权
标题翻译：具有双重厚度的氧化物的垂直导体和平面结构MOS器件以及用于实现具有改进的静态和动态性能以及高缩放密度的功率垂直MOS晶体管的方法
公开(公告)号：US20060186434A1
公开(公告)日：2006-08-24
申请号：US11279967
申请日：2006-04-17
申请人： Angelo MAGRI' , Ferruccio FRISINA , Giuseppe FERLA , Marco CAMALLERI
发明人： Angelo MAGRI' , Ferruccio FRISINA , Giuseppe FERLA , Marco CAMALLERI
IPC分类号： H01L29/423 , H01L21/332
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

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