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1. 发明申请

US20100127729A1 IC TESTING METHODS AND APPARATUS 失效
标题翻译： IC测试方法和设备
公开(公告)号：US20100127729A1
公开(公告)日：2010-05-27
申请号：US12596734
申请日：2008-04-30
申请人： Amir Zjajo
发明人： Amir Zjajo
IPC分类号： G01R31/02
CPC分类号： G01R31/318558
摘要： An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors (14), a threshold circuit (22) for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface (17) for outputting the threshold circuit signal. The process monitoring sensors (14) comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test.
摘要翻译：集成电路包括被测器件和嵌入式测试电路。嵌入式测试电路包括多个过程监控传感器（14），用于将传感器信号与具有上限和下限的阈值窗口进行比较的阈值电路（22）和用于输出阈值电路信号的数字接口（17）。过程监控传感器（14）包括基于所测试设备的电路元件的电路。这种布置使得可以使用嵌入被测器件的过程监控传感器来监控诸如晶体管特性的电路元件性能，使得相同的工艺参数变化适用于被测器件的传感器。传感器优选地与待测设备的物理布局相匹配。

2. 发明申请

US20100109676A1 ANALOG CIRCUIT TESTING AND TEST PATTERN GENERATION 有权
标题翻译：模拟电路测试和测试模式生成
公开(公告)号：US20100109676A1
公开(公告)日：2010-05-06
申请号：US12594967
申请日：2008-04-03
申请人： Amir Zjajo , Jose De Jesus Pineda De Gyvez , Alexander G. Gronthoud
发明人： Amir Zjajo , Jose De Jesus Pineda De Gyvez , Alexander G. Gronthoud
IPC分类号： G01R31/02
CPC分类号： G01R31/31813 , G01R31/316
摘要： Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.
摘要翻译：通过首先选择模拟电路的初始测试输入向量集来选择模拟电路结构测试的测试向量。选择一组故障，其中包括每个对应于模拟电路中的相应节点的故障以及该节点的对应的故障电压值。在模拟电路的测试输出信号值的概率分布中，根据来自所述故障组的每个故障的存在和不存在的测试输入向量，分别计算重叠的度量，作为估计的统计扩展的函数模拟电路中的组件和/或过程参数值。从用于测试的初始测试输入向量组中选择测试输入向量，该测试输入向量基于如果故障低于阈值的至少一个的重叠测量是响应于所选择的测试输入向量在测试选择电脑。

3. 发明授权

US07671618B2 Analog IC having test arrangement and test method for such an IC 有权
标题翻译：具有这种IC的测试布置和测试方法的模拟IC
公开(公告)号：US07671618B2
公开(公告)日：2010-03-02
申请号：US12091026
申请日：2006-10-20
申请人： Amir Zjajo , Hendrik J Bergveld , Rodger F Schuttert , Jose De Jesus Pineda De Gyvez
发明人： Amir Zjajo , Hendrik J Bergveld , Rodger F Schuttert , Jose De Jesus Pineda De Gyvez
IPC分类号： G01R31/26
CPC分类号： G01R31/3167 , G01R31/31721 , G01R31/318536 , G01R31/318575
摘要： An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.
摘要翻译：集成电路（IC）包括多个模拟级（10a-c），每个模拟级与电源（20; 20a-c）导电耦合，并且通过信号路径彼此导电耦合 12）; 以及用于测试所述多个模拟级的测试装置，所述测试装置包括输入装置，例如耦合到来自所述多个模拟级的每个模拟级的信号路径输入的模拟总线（40），输出装置用于将测试结果传送到集成电路的输出的总线（50），用于选择性地禁用模拟级的IC的偏置基础设施中的多个开关（36）等开关装置，以及诸如移位寄存器 60），用于控制切换装置。因此，IC的模拟级可以隔离测试和调试，而不需要通过核的信号路径中的开关。电流传感器（70）可以存在于电源中以便于隔离地对模拟级的结构测试。

4. 发明申请

US20090134904A1 ANALOG IC HAVING TEST ARRANGEMENT AND TEST METHOD FOR SUCH AN IC 有权
标题翻译：具有这种IC的测试布置和测试方法的模拟IC
公开(公告)号：US20090134904A1
公开(公告)日：2009-05-28
申请号：US12091026
申请日：2006-10-20
申请人： Amir Zjajo , Hendrik J. Bergveld , Rodger F. Schuttert , Jose De Jesus Pineda De Gyvez
发明人： Amir Zjajo , Hendrik J. Bergveld , Rodger F. Schuttert , Jose De Jesus Pineda De Gyvez
IPC分类号： G01R31/26
CPC分类号： G01R31/3167 , G01R31/31721 , G01R31/318536 , G01R31/318575
摘要： An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.
摘要翻译：集成电路（IC）包括多个模拟级（10a-c），每个模拟级与电源（20; 20a-c）导电耦合，并且通过信号路径彼此导电耦合 12）; 以及用于测试所述多个模拟级的测试装置，所述测试装置包括输入装置，例如耦合到来自所述多个模拟级的每个模拟级的信号路径输入的模拟总线（40），输出装置用于将测试结果传送到集成电路的输出的总线（50），用于选择性地禁用模拟级的IC的偏置基础设施中的多个开关（36）等开关装置，以及诸如移位寄存器 60），用于控制切换装置。因此，IC的模拟级可以隔离测试和调试，而不需要通过核心的信号路径中的开关。电流传感器（70）可以存在于电源中以便于隔离地对模拟级的结构测试。

5. 发明授权

US08497792B2 Signal generation method and apparatus and test method and system using the same 有权
标题翻译：信号生成方法及装置及其测试方法及系统使用方法
公开(公告)号：US08497792B2
公开(公告)日：2013-07-30
申请号：US13057759
申请日：2009-08-05
申请人： Amir Zjajo
发明人： Amir Zjajo
IPC分类号： H03M1/00
CPC分类号： H03K4/023
摘要： According to a first aspect of the present invention there is provided a signal generation system for generating a predetermined analog signal. The system comprises a clock generator (1) adapted for generating on the basis of an external clock signal a predetermined clock signal, a signal generator including a first gain stage (21) and a second gain stage (22) adapted for providing an overall gain of the signal generator and outputting a stepped analog signal, an analog filter (23) adapted for filtering the stepped analog signal output by the second gain stage and for outputting the predetermined analog signal, and a first and a second clock mapping units (3,4) adapted for receiving the predetermined clock signal, and respectively supplying to the first and second gain stages non-overlapped clock signal, wherein the amount of gain provided by the first and second gain stages is controlled by the non-overlapped clock signals. The present invention further relates to a signal generation method of generating discrete-time periodic analog signals suitable for a built-in self-test, as well as to a test method and system using the same.
摘要翻译：根据本发明的第一方面，提供了一种用于产生预定模拟信号的信号发生系统。该系统包括适于基于外部时钟信号产生预定时钟信号的时钟发生器（1），包括第一增益级（21）和第二增益级（22）的信号发生器，所述第一增益级（21）和第二增益级（22）适于提供总增益并输出阶梯式模拟信号;模拟滤波器，适于对由第二增益级输出的步进模拟信号进行滤波并输出预定的模拟信号;以及第一和第二时钟映射单元， 4），其适于接收所述预定时钟信号，并且分别提供给所述第一和第二增益级非重叠时钟信号，其中由所述非重叠时钟信号控制由所述第一和第二增益级提供的增益量。本发明还涉及产生适于内置自检的离散时间周期模拟信号的信号产生方法，以及使用该测量方法和系统的测试方法和系统。

6. 发明授权

US08310265B2 IC testing methods and apparatus 失效
标题翻译： IC测试方法和仪器
公开(公告)号：US08310265B2
公开(公告)日：2012-11-13
申请号：US12596734
申请日：2008-04-30
申请人： Amir Zjajo , Manuel Jose Barragan Asian , Jose De Jesus Pineda De Gyvez
发明人： Amir Zjajo , Manuel Jose Barragan Asian , Jose De Jesus Pineda De Gyvez
IPC分类号： G01R31/26 , G01R31/3187
CPC分类号： G01R31/318558
摘要： An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors, a threshold circuit for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface for outputting the threshold circuit signal. The process monitoring sensors comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test.
摘要翻译：集成电路包括被测器件和嵌入式测试电路。嵌入式测试电路包括多个过程监控传感器，用于将传感器信号与具有上限和下限的阈值窗口进行比较的阈值电路和用于输出阈值电路信号的数字接口。过程监控传感器包括基于所测试设备的电路元件的电路。这种布置使得可以使用嵌入被测器件的过程监控传感器来监控诸如晶体管特性的电路元件性能，使得相同的工艺参数变化适用于被测器件的传感器。传感器优选地与待测设备的物理布局相匹配。

7. 发明授权

US08122423B2 Analog circuit testing and test pattern generation 有权
标题翻译：模拟电路测试和测试模式生成
公开(公告)号：US08122423B2
公开(公告)日：2012-02-21
申请号：US12594967
申请日：2008-04-03
申请人： Amir Zjajo , Jose De Jesus Pineda de Gyvez , Alexander G. Gronthoud
发明人： Amir Zjajo , Jose De Jesus Pineda de Gyvez , Alexander G. Gronthoud
IPC分类号： G06F17/50
CPC分类号： G01R31/31813 , G01R31/316
摘要： Test vectors for structural testing of an analog circuit are selected by first selecting an initial set of test input vectors for the analog circuit. A set of faults is selected, comprising faults that each correspond to a respective node in the analog circuit and corresponding fault voltage value for that node. A measure of overlap is computed between probability distributions of test output signal values for the analog circuit in response to the test input vectors in the presence and absence of each of the faults from said set of faults respectively, as a function of estimated statistical spread of component and/or process parameter values in the analog circuit. Test input vectors are selected from the initial set of test input vectors for use in testing on the basis of whether the measure of overlap for at least one if the faults is below a threshold value in response to the selected test input vector under control of the test selection computer.
摘要翻译：通过首先选择模拟电路的初始测试输入向量集来选择模拟电路结构测试的测试向量。选择一组故障，其中包括每个对应于模拟电路中的相应节点的故障以及该节点的对应的故障电压值。在模拟电路的测试输出信号值的概率分布中，根据来自所述故障组的每个故障的存在和不存在的测试输入向量，分别计算重叠的度量，作为估计的统计扩展的函数模拟电路中的组件和/或过程参数值。从用于测试的初始测试输入向量组中选择测试输入向量，该测试输入向量基于如果故障低于阈值的至少一个的重叠测量是响应于所选择的测试输入向量在测试选择电脑。

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