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1. 发明申请

US20120210172A1 MULTIPROCESSOR SWITCH WITH SELECTIVE PAIRING 失效
标题翻译：具有选择性配对的多处理器开关
公开(公告)号：US20120210172A1
公开(公告)日：2012-08-16
申请号：US13027882
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/07
CPC分类号： G06F11/1641 , G06F11/1654 , G06F2201/845
摘要： System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.
摘要翻译：用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设设备等。存储器套件通过开关或总线连接到选择性配对设施。

2. 发明申请

US20120210164A1 SCHEDULER FOR MULTIPROCESSOR SYSTEM SWITCH WITH SELECTIVE PAIRING 有权
标题翻译：具有选择性配对的多处理器系统开关调度器
公开(公告)号：US20120210164A1
公开(公告)日：2012-08-16
申请号：US13027960
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/07
CPC分类号： G06F11/1641 , G06F11/165 , G06F2201/845
摘要： System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
摘要翻译：用于在具有选择性配对处理器核心的多处理系统中调度线程的系统，方法和计算机程序产品，用于提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。该方法配置选择性配对设施以使用检查提供一个高度可靠的线程以实现高可靠性，并将线程分配给相应的处理器核心，指示需要进行硬件检查。该方法配置选择性配对工具以提供多个独立核心，并将线程分配给相应的处理器核心，指示固有的弹性。

3. 发明授权

US08930752B2 Scheduler for multiprocessor system switch with selective pairing 有权
标题翻译：具有选择性配对的多处理器系统切换调度程序
公开(公告)号：US08930752B2
公开(公告)日：2015-01-06
申请号：US13027960
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1641 , G06F11/165 , G06F2201/845
摘要： System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
摘要翻译：用于在具有选择性配对处理器核心的多处理系统中调度线程的系统，方法和计算机程序产品，用于提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。该方法配置选择性配对设施以使用检查提供一个高度可靠的线程以实现高可靠性，并将线程分配给相应的处理器核心，指示需要进行硬件检查。该方法配置选择性配对工具以提供多个独立核心，并将线程分配给相应的处理器核心，指示固有的弹性。

4. 发明申请

US20120210162A1 STATE RECOVERY AND LOCKSTEP EXECUTION RESTART IN A SYSTEM WITH MULTIPROCESSOR PAIRING 失效
标题翻译：在具有多处理器配对的系统中的状态恢复和锁定执行重新启动
公开(公告)号：US20120210162A1
公开(公告)日：2012-08-16
申请号：US13027932
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/08 , G06F11/00
CPC分类号： G06F11/1658 , G06F11/1064 , G06F11/1407 , G06F11/1641 , G06F11/1679 , G06F11/203 , G06F11/2043 , G06F2201/845
摘要： System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, wherein the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.
摘要翻译：用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设设备等。存储器套件通过开关或总线连接到选择性配对设施。每个选择性配对的处理器核心包括事务执行设施，其中所述系统被配置为使能处理器回滚到先前状态，并且重新初始化锁步执行，以便当所述选择性配对设施检测到不正确的执行时，从不正确的执行中恢复。

5. 发明授权

US07213123B2 Method and apparatus for mapping debugging information when debugging integrated executables in a heterogeneous architecture 失效
标题翻译：在异构体系结构中调试集成可执行文件时映射调试信息的方法和装置
公开(公告)号：US07213123B2
公开(公告)日：2007-05-01
申请号：US10280243
申请日：2002-10-24
申请人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
发明人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
IPC分类号： G06F12/10
CPC分类号： G06F11/3664 , G06F11/362
摘要： The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping table, wherein the mapping table is read by the dynamic debugger.
摘要翻译：本发明提供了一种用于并行处理环境的动态调试器。这通过在映射表中的运行时动态地更新映射信息来实现，其中映射表被动态调试器读取。

6. 发明授权

US06948082B2 Method and apparatus for software-assisted thermal management for electronic systems 有权
标题翻译：电子系统软件辅助热管理方法和装置
公开(公告)号：US06948082B2
公开(公告)日：2005-09-20
申请号：US10150270
申请日：2002-05-17
申请人： Michael Karl Gschwind , Valentina Salapura
发明人： Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F1/20 , G06F1/32
CPC分类号： G06F1/206 , Y02D10/16
摘要： In a computer system, a device for measuring power dissipation (e.g., using on-die thermal sensors) is linked to both a hardware-based thermal management solution and with a means for causing a notification event to software, so that, initially, the operating system software and/or the application software modifies its behavior in response to the notification event to reduce overall system power dissipation and the hardware-based thermal management solution is only triggered if the software solution is not effective; with both operating system and application software resuming higher-performance algorithms when power dissipation is no longer critical.
摘要翻译：在计算机系统中，用于测量功率消耗的装置（例如，使用片上热传感器）与基于硬件的热管理解决方案和用于使通知事件发生到软件的手段相关联，因此，最初，操作系统软件和/或应用软件响应于通知事件修改其行为以减少整体系统功耗，并且仅当软件解决方案无效时才触发基于硬件的热管理解决方案; 当功耗不再重要时，操作系统和应用软件都会恢复更高性能的算法。

7. 发明授权

US07243333B2 Method and apparatus for creating and executing integrated executables in a heterogeneous architecture 有权
标题翻译：用于在异构架构中创建和执行集成可执行文件的方法和装置
公开(公告)号：US07243333B2
公开(公告)日：2007-07-10
申请号：US10280244
申请日：2002-10-24
申请人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
发明人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F8/451
摘要： The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker compile different segments of the source code for a first and second processor architecture, and generate appropriate stub functions directed at loading code and data to remote nodes so as to cause them to perform operations described by the transmitted code on the data. The compiler and linker generate stub objects to represent remote execution capability, and stub objects encapsulate the transfers necessary to execute code in such environment.
摘要翻译：本发明提供了一种用于编译和链接适用于在异构并行处理器架构上执行的集成可执行程序的编译系统。编译器和链接器为第一和第二处理器架构编译源代码的不同段，并且生成针对加载代码和数据到远程节点的适当的存根功能，以使它们执行由传输的代码对数据描述的操作。编译器和链接器生成存根对象以表示远程执行能力，并且存根对象封装了在这种环境中执行代码所需的传输。

8. 发明授权

US07200840B2 Method and apparatus for enabling access to global data by a plurality of codes in an integrated executable for a heterogeneous architecture 有权
标题翻译：用于通过用于异构架构的集成可执行程序中的多个代码来访问全局数据的方法和装置
公开(公告)号：US07200840B2
公开(公告)日：2007-04-03
申请号：US10280187
申请日：2002-10-24
申请人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
发明人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
IPC分类号： G06F9/45
CPC分类号： G06F9/52
摘要： In the present invention, global information is passed from a first execution environment to a second execution environment, wherein both the first and second processor units comprise separate memories. The global variable is transferred through the invocation of a memory flow controller by a stub function. The global descriptor has a plurality of field indicia that allow a binder to link separate object files bound to the first and second execution environments.
摘要翻译：在本发明中，全局信息从第一执行环境传递到第二执行环境，其中第一和第二处理器单元都包括单独的存储器。全局变量通过存根流程控制器通过存根功能进行调用。全局描述符具有允许绑定链接绑定到第一和第二执行环境的单独对象文件的多个字段标记。

9. 发明授权

US07225431B2 Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture 失效
标题翻译：在异构体系结构中调试集成可执行文件时设置断点的方法和装置
公开(公告)号：US07225431B2
公开(公告)日：2007-05-29
申请号：US10280677
申请日：2002-10-24
申请人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
发明人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
IPC分类号： G06F9/44 , G06F9/45 , G06F15/00 , G06F15/76 , G06F9/30
CPC分类号： G06F11/362
摘要： The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached processor unit. The breakpoint can be inserted directly. Furthermore, the unloaded image of the module can also have a breakpoint associated with it. The breakpoint can be inserted directly into the module image, or a breakpoint request can be generated, and the breakpoint is inserted when the module is loaded into the execution environment of the attached processor unit.
摘要翻译：本发明提供了在并行处理系统中插入和删除断点。断点插入到加载到附加处理器单元的执行环境中的模块中。断点可以直接插入。此外，模块的卸载图像也可以具有与其相关联的断点。断点可以直接插入到模块图像中，或者可以生成断点请求，并且当模块加载到附加的处理器单元的执行环境中时插入断点。

10. 发明授权

US07222332B2 Method and apparatus for overlay management within an integrated executable for a heterogeneous architecture 失效
标题翻译：用于异构架构的集成可执行程序中的覆盖管理的方法和装置
公开(公告)号：US07222332B2
公开(公告)日：2007-05-22
申请号：US10280242
申请日：2002-10-24
申请人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
发明人： Michael Karl Gschwind , Kathryn M. O'Brien , John Kevin O'Brien , Valentina Salapura
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F8/453
摘要： The present invention provides for creating and employing code and data partitions in a heterogeneous environment. This is achieved by separating source code and data into at least two partitioned sections and at least one unpartitioned section. Generally, a partitioned section is targeted for execution on an independent memory device, such as an attached processor unit. Then, at least two overlay sections are generated from at least one partition section. The plurality of partition sections are pre-bound to each other. A root module is also created, associated with both the pre-bound plurality of partitions and the overlay sections. The root module is employable to exchange the at least two overlay sections between the first and second execution environments. The pre-bound plurality of partition sections are then bound to the at least one unpartitioned section. The binding produces an integrated executable.
摘要翻译：本发明提供了在异构环境中创建和使用代码和数据分区。这是通过将源代码和数据分成至少两个分区的部分和至少一个未分区的部分来实现的。通常，划分的部分被定位在独立的存储设备（例如附加的处理器单元）上执行。然后，从至少一个分区部分生成至少两个重叠部分。多个分隔部分彼此预先绑定。还创建了与预先绑定的多个分区和覆盖部分相关联的根模块。根模块可用于在第一和第二执行环境之间交换至少两个重叠部分。然后将预先绑定的多个分割部分绑定到至少一个未分割部分。绑定产生一个集成的可执行文件。

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