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1. 发明申请

WO2010080796A1 EFFICIENT ISOTROPIC MODELING APPROACH TO INCORPORATE ELECTROMAGNETIC EFFECTS INTO LITHOGRAPHIC PROCESS SIMULATIONS 审中-公开
标题翻译：将电磁效应纳入光刻过程模拟的有效的等效建模方法
公开(公告)号：WO2010080796A1
公开(公告)日：2010-07-15
申请号：PCT/US2010/020209
申请日：2010-01-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , AZPIROZ, Jaione, Tirapu , ROSENBLUTH, Alan, E. , GRAUR, Ioana, C.
发明人： AZPIROZ, Jaione, Tirapu , ROSENBLUTH, Alan, E. , GRAUR, Ioana, C.
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/705
摘要： The present invention relates to the modeling of lithographic processes for use in the design of photomasks for the manufacture of semiconductor integrated circuits, and particularly to the modeling of the complex effects due to interaction of the illuminating light with the mask topography. According to the invention, an isofield perturbation to a thin mask representation of the mask is provided by determining, for the components of the illumination, differences between the electric field on a feature edge having finite thickness and on the corresponding feature edge of a thin mask representation. An isofield perturbation is obtained from a weighted coherent combination of the differences for each illumination polarization. The electric field of a mask having topographic edges is represented by combining a thin mask representation with the isofield perturbation applied to each edge of the mask.
摘要翻译：本发明涉及用于制造半导体集成电路的光掩模的设计中使用的光刻工艺的建模，特别涉及由于照明光与掩模形貌的相互作用引起的复杂效应的建模。根据本发明，通过确定对于照明的组件，具有有限厚度的特征边缘上的电场与薄掩模的相应特征边缘之间的差异来确定对掩模的薄掩模表示的异场扰动表示。从每个照明偏振的差异的加权相干组合获得异场扰动。通过将薄掩模表示与施加到掩模的每个边缘的异场扰动组合来表示具有形貌边缘的掩模的电场。

2. 发明申请

WO2007140130A2 N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：包含双重压力机的N沟道MOSFET及其形成方法
公开(公告)号：WO2007140130A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069100
申请日：2007-05-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LI, Jinghong, H. , LIU, Yaocheng , LUO, Zhijiong , MADAN, Anita , ROVEDO, Nivo
发明人： LI, Jinghong, H. , LIU, Yaocheng , LUO, Zhijiong , MADAN, Anita , ROVEDO, Nivo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括第一和第二图案应力层，它们都包含碳取代和拉伸应力的单晶半导体。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区。具有不同碳浓度和不同深度的第一和第二图案应力层的这种n-FET提供了改进的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

3. 发明申请

WO2005050701A2 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 审中-公开
标题翻译：具有颗粒半导体材料的应力半导体器件结构
公开(公告)号：WO2005050701A2
公开(公告)日：2005-06-02
申请号：PCT/US2004/037434
申请日：2004-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , BELYANSKY, Michael, P. , BOYD, Diane, C. , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg
发明人： DORIS, Bruce, B. , BELYANSKY, Michael, P. , BOYD, Diane, C. , CHIDAMBARRAO, Dureseti , GLUSCHENKOV, Oleg
IPC分类号： H01L
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

4. 发明申请

WO2003036449A1 METHOD AND APPARATUS FOR CONTROLLING DATA RATE ON A FORWARD CHANNEL IN A WIRELESS COMMUNICATION SYSTEM 审中-公开
标题翻译：用于在无线通信系统中控制前向信道上的数据速率的方法和装置
公开(公告)号：WO2003036449A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/033833
申请日：2002-10-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： SMITH, Jack, Robert , VENTRONE, Sebastian, Theodore
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： In a first aspect, a method is provided for conserving power in a processing integrated circuit. This method includes the steps of calculating (401-408) power consumption for executing an instruction and data corresponding to the instruction; and executing (409, 410) the instruction if such execution does not exceed a predetermined power level. In a second aspect, a method is provided for conserving power in a processing integrated circuit employing a plurality of execution units. The method includes the steps of comparing (301, 302) a total power to be consumed by the processing integrated circuit to a power budget for the processing integrated circuit; and if the total power exceeds the power budget, freezing (304) execution of an instruction by one of the plurality of execution units so as to allow execution of the instruction to continue at a later time from where execution waSt frozen. Numerous other aspects are provided, as are systems and apparatus.
摘要翻译：在第一方面，提供了一种用于在处理集成电路中节省功率的方法。该方法包括计算（401-408）用于执行指令的功耗和对应于该指令的数据的步骤; 以及如果所述执行不超过预定功率电平则执行（409,410）所述指令。在第二方面，提供一种用于在采用多个执行单元的处理集成电路中节省功率的方法。该方法包括以下步骤：将处理集成电路要消耗的总功率（301,302）与处理集成电路的功率预算进行比较; 并且如果所述总功率超过所述功率预算，则通过所述多个执行单元中的一个来执行指令的冻结（304），从而允许执行所述指令在从执行waSt被冻结的较后时间继续执行。还提供了许多其他方面，系统和装置也是如此。

5. 发明申请

WO2014159391A1 DIELECTRIC VOID ETCHED IN FINFET SACRIFICIAL LAYER 审中-公开
标题翻译：在FINFET SACFIFICIAL层中刻蚀电介质
公开(公告)号：WO2014159391A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/023379
申请日：2014-03-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： WANG, Yanfeng , GUO, Dechao , LU, Darsen , OLDIGES, Philip , WANG, Gan , WANG, Xin
IPC分类号： H01L21/335 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/823481 , H01L21/823878 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/78 , H01L29/7842 , H01L29/7848 , H01L29/785
摘要： A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.
摘要翻译：公开了一种finFET和制造方法。牺牲层形成在体半导体衬底上。顶层半导体层（如硅）被设置在牺牲层上。体半导体衬底凹陷在与晶体管栅极相邻的区域中，并且在凹陷区域中形成应力层。选择性地去除牺牲层并用诸如可流动氧化物的绝缘体代替。绝缘体在不使用掺杂剂的情况下提供了晶体管沟道和体衬底之间的隔离。

6. 发明申请

WO2010111345A1 SELF-FORMING TOP ANTI-REFLECTIVE COATING COMPOSITIONS AND, PHOTORESIST MIXTURES AND METHOD OF IMAGING USING SAME 审中-公开
标题翻译：自形成顶部防反射涂料组合物和光刻胶混合物及其成像方法
公开(公告)号：WO2010111345A1
公开(公告)日：2010-09-30
申请号：PCT/US2010/028430
申请日：2010-03-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HUANG, Wu-Song , POPOVA, Irene , VARANASI, Pushkara, Rao , VYKLICKY, Libor
发明人： HUANG, Wu-Song , POPOVA, Irene , VARANASI, Pushkara, Rao , VYKLICKY, Libor
IPC分类号： C07C409/22 , G03C1/00
CPC分类号： C08F212/34 , C08F212/32 , C08F220/22 , C08F220/26 , C08F220/28 , G03F7/0046 , G03F7/0392 , G03F7/091
摘要： A composition of matter. The composition of matter includes a polymer having an ethylenic backbone and comprising a first monomer having an aromatic moiety, a second monomer having a base soluble moiety or an acid labile protected base soluble moiety, and a third monomer having a fluoroalkyl moiety. Also a photoresist formulation including the composition of matter and a method of imaging using the photoresist formulation including the composition of matter.
摘要翻译：物质的组成。物质的组成包括具有乙烯主链并包含具有芳族部分的第一单体，具有碱可溶部分的第二单体或酸不稳定保护基可溶部分的第一单体和具有氟代烷基部分的第三单体的聚合物。还包括包含物质组合物的光致抗蚀剂制剂和使用包含物质组成的光致抗蚀剂制剂的成像方法。

7. 发明申请

WO2008088992A2 METHOD FOR ENHANCING THE DIAGNOSTIC ACCURACY OF A VLSI CHIP 审中-公开
标题翻译：用于增强VLSI芯片诊断精度的方法
公开(公告)号：WO2008088992A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/050595
申请日：2008-01-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KUSKO, Mary, P. , MAIER, Gary, W. , MOTIKA, Franco , TRAN, Phong, T.
发明人： KUSKO, Mary, P. , MAIER, Gary, W. , MOTIKA, Franco , TRAN, Phong, T.
IPC分类号： G06F11/26
CPC分类号： G06F11/261
摘要： A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data (10) drives adaptive test methods which hone the test pattern set (530) and fail data collection (10) for successful diagnostic resolution. Environmentally based fail data (620) is used in diagnostic simulation (600) to achieve a more accurate environmentally based fault callout (40). When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation (520) methods are employed to result in enhanced diagnostic resolution.
摘要翻译：适用于VLSI设计的诊断过程，以解决诊断解决的准确性。基于环境的故障数据（10）驱动磨合测试模式集（530）和故障数据收集（10）的自适应测试方法，以成功诊断分辨率。基于环境的故障数据（620）用于诊断模拟（600），以实现更准确的基于环境的故障标注（40）。当需要时，该过程中将包含其他信息，以进一步完善和定义模拟或标注结果。类似地，根据需要采用自适应测试模式生成（520）方法来提高诊断分辨率。

8. 发明申请

WO2007127770A2 IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译：改进的具有双栅导体的CMOS二极管及其形成方法
公开(公告)号：WO2007127770A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/067361
申请日：2007-04-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
发明人： ONSONGO, David, M. , RAUSCH, Werner , YANG, Haining, S.
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L29/66356
摘要： The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.
摘要翻译：本发明提供了具有双栅极导体的改进的CMOS二极管结构。具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度导体。

9. 发明申请

WO2007038237A2 MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
标题翻译：在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流
公开(公告)号：WO2007038237A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/036916
申请日：2006-09-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , DOKUMACI, Omer , GLUSCHENKOV, Oleg , BELYANSKY, Michael
发明人： CHIDAMBARRAO, Dureseti , DOKUMACI, Omer , GLUSCHENKOV, Oleg , BELYANSKY, Michael
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/512 , H01L21/26586 , H01L21/31155 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.
摘要翻译：本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。

10. 发明申请

WO2004049406A1 STRAINED FINFET CMOS DEVICE STRUCTURES 审中-公开
标题翻译：应变FINFET CMOS器件结构
公开(公告)号：WO2004049406A1
公开(公告)日：2004-06-10
申请号：PCT/US2002/037931
申请日：2002-11-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DORIS, Bruce, B. , CHIDAMBARRAO, Dureseti , IEONG, Meikei , MANDELMAN, Jack, A.
发明人： DORIS, Bruce, B. , CHIDAMBARRAO, Dureseti , IEONG, Meikei , MANDELMAN, Jack, A.
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823828 , H01L27/092 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).
摘要翻译：一种半导体器件结构，包括PMOS器件（200）和设置在衬底（1,2）上的NMOS器件（300），该PMOS器件包括压迫PMOS器件的有源区的压缩层（6），NMOS器件包括施加NMOS器件的有源区的拉伸层（9），其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件是FinFET器件（200,300）。

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