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1. 发明申请

US20130304450A1 Method for Unified High-Level Hardware Description Language Simulation Based on Parallel Computing Platforms 审中-公开
标题翻译：基于并行计算平台的统一高级硬件描述语言模拟方法
公开(公告)号：US20130304450A1
公开(公告)日：2013-11-14
申请号：US13887636
申请日：2013-05-06
申请人： STARDFX TECHNOLOGIES, INC.
发明人： Tso-Sheng Tsai , Laung-Terng Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method to build a unified simulator for simulating a design on a parallel computing platform. The parallel computing platform comprises two or more (processors) cores which are deemed as an integral part of the unified simulator. The design is modeled in a high-level hardware description language. The design is first translated into a set of elements each comprising one or more simulation operations. Simulation operations from elements are next assigned, dynamically or statically, to one or more cores in a central processing unit (CPU) or in a multi-core system on the parallel computing platform to perform a parallel logic or fault simulation. Multiple (simulation) operation processing systems are used to process simulation operations in parallel. Simulation data in each element is managed to be self-contained so a fine-grained parallelism among multiple cores is achieved. Multiple communication links are available to enable the unified simulator to work with other third-party software to create new applications.
摘要翻译：一种用于在并行计算平台上模拟设计的统一模拟器的方法。并行计算平台包括被认为是统一模拟器的组成部分的两个或多个（处理器）核心。该设计以高级硬件描述语言建模。该设计首先被翻译成一组元素，每个元素包括一个或多个模拟操作。来自元件的仿真操作将被动态地或静态地分配给中央处理单元（CPU）中的一个或多个核心，或并行计算平台上的多核系统中，以执行并行逻辑或故障模拟。多个（模拟）操作处理系统被用于并行处理仿真操作。每个元素中的仿真数据被管理为独立的，从而实现多个核心之间的细粒度并行性。多个通信链接可用于使统一模拟器与其他第三方软件一起工作，以创建新的应用程序。

2. 发明授权

US08402328B2 Apparatus and method for protecting soft errors 有权
标题翻译：用于保护软错误的装置和方法
公开(公告)号：US08402328B2
公开(公告)日：2013-03-19
申请号：US12509019
申请日：2009-07-24
申请人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang
发明人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang
IPC分类号： G01R31/28
CPC分类号： G01R31/31816 , G01R31/318544 , G06F17/505 , G06F2217/14
摘要： An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.
摘要翻译：用于进行制造测试操作，慢速快照操作，慢速签名分析操作，速度特征分析操作，缺陷容差操作或缺陷容错操作的能力的软错误恢复或校正的装置和方法以上操作的任意组合。在一个实施例中，一种装置包括用于软错误弹性的系统电路，阴影电路和输出接合电路。耦合到系统电路和阴影电路的输出端子的输出接合电路至少包括用于缺陷容限的S元件。在另一个实施例中，一种装置包括系统电路，阴影电路，调试电路和用于软错误校正的输出连接电路。耦合到系统电路，阴影电路和调试电路的输出端子的输出接合电路至少包括用于缺陷容差的V元件。

3. 发明申请

US20150254383A1 METHOD FOR CONCURRENT SIMULATION TO EVALUATE THE TEST QUALITY OF INTEGRATED CIRCUITS AND COMPUTER PROGRAM 审中-公开
标题翻译：综合仿真评估综合电路和计算机程序测试质量的方法
公开(公告)号：US20150254383A1
公开(公告)日：2015-09-10
申请号：US14615949
申请日：2015-02-06
申请人： StarDFX Technologies, Inc.
发明人： TSAI TSO-SHENG , WANG Laung-Terng , HYOUNG-KOOK KIM
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045 , G06F2217/04
摘要： A method to evaluate the quality of testbenches using concurrent simulation for functional verification or fault simulation of a digital circuit in an integrated circuit or a system is described. The digital circuit is modeled in a high-level hardware description language. Mutations can be thought of as artificial bugs or design faults which are described at a behavioral or system level. A computer first reads in the digital circuit. Mutations are then inserted into the circuit model that describes the digital circuit. Simulation of multiple mutations is finally performed concurrently to check whether each inserted mutation has generated an output value which is different from a reference value. The reference value may be generated internally from the digital circuit or testbenches, or generated externally from an independent reference system. The reference system may be a hardware accelerator or an identical design developed independent of the circuit model to meet the design's specifications. The concurrent simulation method also applies to software testing of computer programs.
摘要翻译：描述了使用集成电路或系统中的数字电路的功能验证或故障模拟的并发仿真来评估测试台的质量的方法。数字电路以高级硬件描述语言建模。突变可以被认为是在行为或系统级别描述的人为错误或设计错误。计算机首先读入数字电路。然后将突变插入描述数字电路的电路模型中。多个突变的模拟最终同时进行，以检查每个插入的突变是否已经产生了与参考值不同的输出值。参考值可以从数字电路或测试台内部产生，或者从独立参考系统外部产生。参考系统可以是独立于电路模型开发的硬件加速器或相同的设计，以满足设计的规格。并发仿真方法也适用于计算机程序的软件测试。

4. 发明授权

US08418100B2 Robust scan synthesis for protecting soft errors 有权
标题翻译：用于保护软错误的强大的扫描合成
公开(公告)号：US08418100B2
公开(公告)日：2013-04-09
申请号：US13416529
申请日：2012-03-09
申请人： Laung-Terng Wang , Nur A. Touba , Shianling Wu , Ravi Apte
发明人： Laung-Terng Wang , Nur A. Touba , Shianling Wu , Ravi Apte
IPC分类号： G06F17/50
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：用于在用于在系统中生成鲁棒扫描设计的设计上进行软错误保护的鲁棒扫描合成的方法在寄存器传送级（RTL）或门级选择性地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

5. 发明申请

US20120173940A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20120173940A1
公开(公告)日：2012-07-05
申请号：US13416529
申请日：2012-03-09
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：用于在用于在系统中生成鲁棒扫描设计的设计上进行软错误保护的鲁棒扫描合成的方法在寄存器传送级（RTL）或门级选择性地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

6. 发明授权

US08161441B2 Robust scan synthesis for protecting soft errors 有权
标题翻译：用于保护软错误的强大的扫描合成
公开(公告)号：US08161441B2
公开(公告)日：2012-04-17
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng Wang , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G06F17/50
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

7. 发明申请

US20110022908A1 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS 有权
标题翻译：用于保护软件错误的稳健扫描合成
公开(公告)号：US20110022908A1
公开(公告)日：2011-01-27
申请号：US12508977
申请日：2009-07-24
申请人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
发明人： Laung-Terng WANG , Nur A. Touba , Zhigang Jiang , Shianling Wu , Ravi Apte
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31816 , G06F17/505 , G06F2217/14
摘要： A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.
摘要翻译：一种用于在用于在系统中生成鲁棒扫描设计的设计上执行用于软错误保护的鲁棒扫描合成的方法。系统在寄存器传输级（RTL）或门级有选择地建模; 该设计至少包括用于映射到选择鲁棒扫描单元类型的鲁棒扫描单元的顺序元件或扫描单元。该方法包括基于用于在设计数据库上合成鲁棒扫描单元的给定控制信息文件在设计数据库上执行扫描替换和扫描缝合; 并以预定的RTL或预定的门级产生合成的鲁棒扫描设计。

8. 发明申请

US20110022907A1 FPGA Test Configuration Minimization 审中-公开
标题翻译： FPGA测试配置最小化
公开(公告)号：US20110022907A1
公开(公告)日：2011-01-27
申请号：US12689791
申请日：2010-01-19
申请人： Zhigang Jiang , Shianling Wu , Samy Makar , Laung-Terng Wang
发明人： Zhigang Jiang , Shianling Wu , Samy Makar , Laung-Terng Wang
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318519
摘要： A method for automatically generating test patterns using a close-to-minimum number of configurations for a Field Programmable Gate Array (FPGA) to reduce test data volume and test application time. The FPGA can be a standalone programmable device or a circuit embedded in an Application Specific Integrated Circuit (ASIC).
摘要翻译：一种用于使用现场可编程门阵列（FPGA）的接近最小数量的配置来自动生成测试模式的方法，以减少测试数据量并测试应用时间。 FPGA可以是独立的可编程器件或嵌入在专用集成电路（ASIC）中的电路。

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