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    • 87. 发明公开
    • Semiconductor device
    • Halbleiterbauelement。
    • EP0123936A1
    • 1984-11-07
    • EP84103566.0
    • 1984-03-30
    • HITACHI, LTD.
    • Horiuchi, MasatadaYamaguchi, Ken
    • H01L29/08H01L29/50H01L27/08H01L29/62
    • H01L29/0847H01L21/2257H01L21/823835H01L27/0927H01L29/41783H01L29/456H01L29/66575H01L29/66628
    • Disclosed is a semiconductor device, especially MISFET, which can ensure high breakdown voltage and operate at high speed. The source and drain regions (5, 6; 24, 25) have an impurity concentration not exceeding 10 20 cm -3 , and on the surface of the impurity regions there is a metal silicide layer (12, 214) with a very thin, highly conductive layer (13) formed underneath the silicide. In the case of CMOS, the impurity concentration of the n-type drain or source regions (24, 25) does not exceed 10 20 cm -3 whereas the impurity concentration of an p-type drain or source regions does not exceed 10 19 cm -3 and at least one portion (214) of the drain or source region (24,25) is made of a metal silicide, thereby effectively preventing the latch-up phenomenon. The characteristics of the MISFET may be further improved by having a gate sidewall insulator of a high dielectric constant.
    • 公开了一种可以确保高击穿电压并以高速运行的半导体器件,尤其是MISFET。 源区和漏区(5,6; 24,25)的杂质浓度不超过10 2 cm -3,在杂质区的表面上有金属硅化物层( 12,214),其具有形成在硅化物下方的非常薄的高导电层(13)。 在CMOS的情况下,n型漏极或源极区(24,25)的杂质浓度不超过10 2 cm -3,而p型漏极的杂质浓度 或源极区域不超过10 9 cm -3且漏极或源极区域(24,25)的至少一部分(214)由金属硅化物制成,从而有效地防止了 闭锁现象。 通过具有高介电常数的栅极侧壁绝缘体可以进一步改善MISFET的特性。
    • 89. 发明专利
    • SOLID-STATE IMAGE SENSING DEVICE
    • JPH0697415A
    • 1994-04-08
    • JP24630192
    • 1992-09-16
    • MATSUSHITA ELECTRONICS CORP
    • MIZOUCHI CHIHIRO
    • H01L27/148H01L29/417H01L29/50
    • PURPOSE:To make it possible to increase a charge transfer capacity of a transfer electrode next to a charge detection part without degrading charge transfer efficiency. CONSTITUTION:A first transfer electrode 2A which is adjacent to a charge detection part 1 is formed in the shape of an arc. Due to this. a maximum transfer distance of signal charges in a lower part of the first transfer electrode 2A in a charge transfer channel 9 is equivalent to a gate length of the first transfer electrode 2A and the gate length is increased more than required, which serves to protect the transfer efficiency of the first transfer electrode 2A on its lower part from being degraded. In addition to that, a part connected to the charge detection part 1 in the charge transfer channel 9 is formed to keep the same width with the other parts in the charge detection channel 9. Therefore, this construction increases a transfer capacity of signal charges compared with the charge transfer channel 9 which is reduced in tapered shape in a part connected to the charge detection part.
    • 90. 发明专利
    • SCHOTTKY TYPE FIELD EFFECT TRANSISTOR
    • JPH0653250A
    • 1994-02-25
    • JP20635692
    • 1992-08-03
    • NEC CORP
    • MORIKAWA HIROSHI
    • H01L29/872H01L21/338H01L29/417H01L29/47H01L29/812H01L29/48H01L29/50
    • PURPOSE:To make it possible to increase an output power by increasing a current between a drain and a source when a high frequency voltage is applied to a gate and decreasing the density of the levels having a slow time constant existing at the interface of an active layer by the formation of a metallic film having a Schottky contact with the active layer between a gate electrode and a drain electrode. CONSTITUTION:A gate electrode 2 formed in Schottky contact with an active layer 1 of the surface portion of a compound semiconductor substrate 9 is provided together with a source electrode 4s and a drain electrode 4d formed in ohmic contact with the active layer 1 at a predetermined distance between them on both sides of the gate electrode 2. In such an FET, a metal film 5 in Schottky contact with the active layer 1 is formed between the gate electrode 2 and the drain electrode 4d. For instance, the gate electrode 2 made of WSix is formed on the N-type active layer 1 on the surface portion of a semi- insulation GaAs substrate 9, and the metal layer 5 such as WSix is formed on the N type active layer 1 between the gate electrode 2 and N layer 3d on at the side of the drain electrode 4d.