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81. 发明公开

EP0558856A2 A method for producing a semiconductor laser device 失效
标题翻译： Herstellungsverfahrenfüreinen Halbleiterlaser。
公开(公告)号：EP0558856A2
公开(公告)日：1993-09-08
申请号：EP92311823.6
申请日：1992-12-24
申请人： SHARP KABUSHIKI KAISHA
发明人： Watanabe, Masanori , Ohbayashi, Ken , Sasaki, Kazuaki , Yamamoto, Osamu , Matsumoto, Mitsuhiro
IPC分类号： H01S3/025
CPC分类号： H01S5/0425 , H01S5/0201 , H01S5/0281 , H01S5/164 , Y10S148/026 , Y10S148/095 , Y10S148/104 , Y10S148/106 , Y10S148/143 , Y10S438/945
摘要： A method for producing a semiconductor laser device includes the steps of: forming semiconductor window layers on either one of a top surface of an internal structure or a reverse surface of a substrate (10) and on light-emitting end facets (30A,30B) of the internal structure; forming a reflection film (34) on the light-emitting end facets; removing the window layer formed on either one of the top surface or the reverse surface by using an etchant which hardly etches the reflection film; and forming electrodes on the surface from which the window layer is removed by etching and on the other surface. Another method for producing a semiconductor laser device includes the steps of: forming semiconductor window layers on light-emitting end facets of the bars (2); inserting the bars (2) into an apparatus having openings for forming electrodes and a supporting portion for preventing a positional shift between the bars (2) and the openings, and forming the electrodes on the top surfaces and the reverse surfaces of the bars (2); and cutting the bars (2) into the chips.
摘要翻译：一种制造半导体激光器件的方法包括以下步骤：在内部结构的顶表面或衬底（10）的背面和发光端面（30A，30B）上的任一个上形成半导体窗口层，的内部结构; 在发光端面上形成反射膜（34）; 通过使用几乎不蚀刻反射膜的蚀刻剂去除形成在顶表面或反面中的任一个上的窗口层; 以及在通过蚀刻除去窗口层的表面上形成电极，并在另一个表面上形成电极。制造半导体激光器件的另一种方法包括以下步骤：在条（2）的发光端面上形成半导体窗口层; 将杆（2）插入具有用于形成电极的开口的装置和用于防止杆（2）和开口之间的位置偏移的支撑部分，并且在杆（2）的顶表面和反面上形成电极）; 并将条（2）切割成芯片。

82. 发明授权

EP0223994B1 Method of forming a sub-micrometer trench structure on a semiconductor substrate 失效
标题翻译：在半导体基板上形成副微结构的结构的方法
公开(公告)号：EP0223994B1
公开(公告)日：1993-03-17
申请号：EP86114062.2
申请日：1986-10-10
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Schulz, Ronald Norman
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31116 , Y10S438/945 , Y10S438/951

83. 发明公开

EP0460440A2 Method of forming a localized buried isolation structure 失效
标题翻译：用于超高能量注入和使用这种方法的用于局部埋入注入和隔离结构Selbstaligniertes标记方法。
公开(公告)号：EP0460440A2
公开(公告)日：1991-12-11
申请号：EP91108017.4
申请日：1991-05-17
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Aronowitz, Sheldon , Hart, Courtney L. , Buynoski, Matthew
IPC分类号： H01L21/266 , H01L21/76 , H01L21/316
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/266 , H01L21/31662 , H01L21/74 , Y10S438/945 , Y10S438/95 , Y10S438/966
摘要： A self-aligned masking process for use with ultra-high energy implants (implant energies equal to or greater than 1 MeV) is provided. The process can be applied to an arbitrary range of implant energies. Consequently, high doses of dopant may be implanted to give high concentrations that are deeply buried. This can be coupled with the fact that amorphization of the substrate lattice is relatively localized to the region where the ultra-high energy implant has peaked to yield a procedure to form buried, localized isolation structures.
摘要翻译：提供了一种用于超高能量植入物（植入能量等于或大于1兆电子伏）中使用的自对准掩模工艺。该方法可在植入能量的任意范围被应用于。因此，高剂量的掺杂剂的可植入给予高浓度也被深埋。这可与基板的晶格的factthat非晶化相对定位于其中所述超高能植入物已经达到顶峰，得到一个过程来形成掩埋区域中，局部的隔离结构。

84. 发明公开

EP0349070A3 A method of manufacturing a semiconductor device 失效转让
公开(公告)号：EP0349070A3
公开(公告)日：1991-02-20
申请号：EP89201658.5
申请日：1989-06-23
申请人： Philips Electronics N.V.
发明人： Bellersen, Michael Friedrich Bruno , Gootzen, Wilhelmus Franciscus Marie , Van Laarhoven, Josephus Martin Franciscus Gerardus , Doan, Trung Tri
IPC分类号： H01L21/033 , H01L21/28 , H01L21/285 , H01L21/321 , H01L21/90
CPC分类号： H01L21/32136 , H01L21/76804 , H01L21/76885 , Y10S438/945
摘要： Spaced-apart regions (2) each having top (2a) and side walls (2b) meeting at an edge (20) are defined on a surface (1a) of a substructure (1) forming part of the device. A layer (3) of insulating material is provided over the said surface (1a) and regions (2), so that the insulating material is provided preferentially at the said edges (20) of the regions (2) to form adjacent the said edges (20) portions (31) of the insulating material which overhang the underlying insulating material (32) provided on the said surface (1a). The insulating material layer (3) is then etched anisotropically to expose the top walls (2a). During the anisotropic etching the overhanging portions (31) initially mask the underlying insulating material provided on the said surface (1a) so that the etching of the underlying insulating material is controlled by the etching away of the overhanging portions (31) and when the top walls (2a) are exposed relatively gently sloping spacers or portions (30) of the insulating material remain on the side walls (2b). A further insulating material layer (4) may then be provided over the structure.

85. 发明公开

EP0384145A1 Multilevel resist plated transfer layer process for fine line lithography 失效
标题翻译： Feinstruktur-Litographieverfahren unter Verwendung von Fotolackschichten und einer plattierten Transferschicht。
公开(公告)号：EP0384145A1
公开(公告)日：1990-08-29
申请号：EP90101421.7
申请日：1990-01-24
申请人： Hewlett-Packard Company
发明人： Studebaker, Lawrence G. , Wong, Edward H.
IPC分类号： H01L21/027 , H01L29/812 , H01L21/28 , H01L21/328
CPC分类号： H01L29/66863 , H01L21/0272 , H01L21/31144 , Y10S148/10 , Y10S148/105 , Y10S148/143 , Y10S438/945 , Y10S438/947 , Y10S438/949
摘要： A multilevel resist process for fine line e-beam lithography, or, alternatively, deep ultraviolet (DUV) optical lithography with a clear field mask involving the use of a plated transfer layer for image reversal. The process preferably uses a high brightness, quarter-micron diameter electron beam and a high speed negative resist to fabricate microwave MESFETs, MODFETS, and integrated circuits with gate lengths of 0.25 micron and below. This is achieved by producing a line of negative resist which can be developed to 0.25 micron or below. A plated transfer layer is then applied which provides image reversal, converting the line of resist into an opening suitable for conventional gate recess etching, gate metal deposition, and lift-off. A positive resist can be substituted for the negative e-beam resist and exposed with DUV through a clear field mask instead of an electron beam for the fabrication of MESFETs.
摘要翻译：用于细线电子束光刻的多层抗蚀剂工艺，或者具有涉及使用电镀转移层进行图像反转的清晰场屏蔽的深紫外（DUV）光刻。该工艺优选使用高亮度，四分之一微米直径的电子束和高速负抗蚀剂来制造微米MESFET，MODFET和栅极长度为0.25微米及以下的集成电路。这是通过生产可以显影至0.25微米或更低的负性抗蚀剂线来实现的。然后施加电镀转印层，其提供图像反转，将抗蚀剂线转换成适合于常规栅极凹槽蚀刻，栅极金属沉积和剥离的开口。正抗蚀剂可以代替负电子束抗蚀剂，并通过清除场掩膜而不是用于制造MESFET的电子束用DUV曝光。

86. 发明公开

EP0223994A3 Method of forming a sub-micrometer trench structure on a semiconductor substrate 失效
标题翻译：防止非均衡蚀刻的方法在低分辨率范围内的图像转印
公开(公告)号：EP0223994A3
公开(公告)日：1989-10-25
申请号：EP86114062.2
申请日：1986-10-10
申请人： International Business Machines Corporation
发明人： Ogura, Seiki , Riseman, Jacob , Rovedo, Nivo , Schulz, Ronald Norman
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/31116 , Y10S438/945 , Y10S438/951
摘要： In the process of sidewall image transfer, a vertical step is etched in some material and then a conformal layer of some other material is deposited over the step. By reactive ion etching the conformal material can be anisotropically etched which results in a sidewall spacer of the second material on the vertical surfaces of the step material. By removing the step material, the free standing spacer can then be used as a mask. One area in which improvement is desired is in the selectivity of the etch of the spacer to the material immediately below it. Because of the limited number of materials and reactive ion etching gases it is difficult to avoid an etch in the underlying layer as the sidewall spacer is formed. A suitable etch stop is employed beneath the step material to avoid the problem. Because of the usual technology, the spacer material is plasma deposited silicon nitride and the step material is photoresist. Polysilicon, aluminum or similar metal is employed as an etch stop, since it is not affected by a CF₄ based gas which is used to form the spacer.

87. 发明公开

EP0275595A1 Procédé de réalisation d'interconnexions et de croisements entre niveaux de métallisation d'un circuit intégré 失效
标题翻译：一种用于化合物系和不同的金属化的交叉点的集成电路上的制备方法。
公开(公告)号：EP0275595A1
公开(公告)日：1988-07-27
申请号：EP87202546.5
申请日：1987-12-16
申请人： LABORATOIRES D'ELECTRONIQUE PHILIPS , Philips Electronics N.V.
发明人： Rabinzohn, Patrick Société Civile S.P.I.D.
IPC分类号： H01L21/90 , H01L21/31
CPC分类号： H01L21/76819 , H01L21/31055 , H01L21/76804 , H01L21/76838 , Y10S438/945
摘要： Procédé de réalisation d'interconnexions et de croisements entre niveaux de métallisation d'un circuit intégré dans lequel la formation d'un premier niveau métallique (a) est suivie du dépôt d'une première et d'une deuxième couche isolantes (b et c), d'une gravure sélective de la deuxième couche isolante vis à vis de la première (d), de la planarisation de la structure ainsi obtenue par une couche sacrifiée (e), de la gravure de cette couche sacrifiée jusqu'au niveau de la deuxième couche isolante (f), de la gravure sélective entre ces différentes couches de façon à déboucher sur le premier niveau métallique en regard d'une métallisation et à assurer simultanément l'isolement entre niveaux métalliques en regard d'un croisement (g), et enfin de la réalisation du second niveau métallique (h). Ce procédé de quasi autoalignement élimine une étape photolithographique et assure un gain appréciable en densité d'intégration et en fiabilité du circuit.
Application aux circuits intégrés à plusieurs niveaux de métallisation.

88. 发明公开

EP0137927A3 Process for the controlled etching of tapered vias in borosilicate glass dielectrics 失效
标题翻译：硼酸盐玻璃电极中控制镉蚀刻的工艺
公开(公告)号：EP0137927A3
公开(公告)日：1988-03-23
申请号：EP84108710
申请日：1984-07-24
申请人： International Business Machines Corporation
发明人： Powell, Jimmie L. , Standley Charles L. , Suierveld, John
IPC分类号： H01L21/31 , H01L21/60
CPC分类号： H01L21/76804 , C03C15/00 , H01L21/31111 , H01L21/31144 , Y10S438/945
摘要： @ A process for forming via openings (60) in a relatively thick layer (50) of borosilicate glass while controlling the degree of taper of the side walls of the opening to be not less than 45° by (1) depositing a layer of silicon nitride that contains silicon in an amount in excess of stoichiometric in Si 3 N 4 (2) densifying the silicon nitride layer, (3) depositing a layer of resist, (4) exposing and developing the layer of resist to define a desired pattern of openings in the borosilicate glass layer, (5) removing the exposed silicon nitride areas, and (6) subjecting the resultant exposed borosilicate glass surface to an etchant for the glass.

89. 发明公开

EP0214514A3 Mask removal tool 失效
标题翻译：掩模拆卸工具
公开(公告)号：EP0214514A3
公开(公告)日：1988-01-07
申请号：EP86111466
申请日：1986-08-19
申请人： International Business Machines Corporation
发明人： Burns, Richard W.
IPC分类号： G03B41/00 , G03F01/00
CPC分类号： G03F7/707 , Y10S156/93 , Y10S438/942 , Y10S438/945 , Y10T29/49821 , Y10T29/53274 , Y10T156/1179 , Y10T156/1189 , Y10T156/19
摘要： An apparatus 10 for removing a mask 11 which extends beyond the outer edges of a semiconductor wafer 12 bonded thereto. The apparatus includes a base 22 having a vacuum chamber 26 opening onto the upper surface of the base, a vacuum valve 20 separating the vacuum chamber 26 from a vacuum source 21, an actuating lever 16 and a mask discharge facilitator 27. The discharge facilitator 27 comprises a horizontal plate 19 having a plurality of vertical pins 18 around the periphery thereof. When the lever 16 is actuated, it opens the vacuum valve and lifts the discharge facilitator forcing the vertical pins 18 into contact with the mask 11. The simultaneous application of the vacuum holding force, and vertical force applied by the pins causes the separation of the mask from the upper surface of the wafer.

90. 发明授权

EP0054641B1 Thermally compensated shadow mask 失效
标题翻译：热补偿阴影面膜
公开(公告)号：EP0054641B1
公开(公告)日：1985-02-13
申请号：EP81108132.2
申请日：1981-10-09
申请人： International Business Machines Corporation
发明人： Stuby, Kenneth Paul
IPC分类号： G03F9/00
CPC分类号： G03F7/70433 , C23C14/042 , G03F9/00 , H01L21/682 , Y10S438/945

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