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81. 发明授权

US08674745B2 Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit 有权
标题翻译：电平转换电路和采用电平转换电路的半导体集成电路器件
公开(公告)号：US08674745B2
公开(公告)日：2014-03-18
申请号：US13406715
申请日：2012-02-28
申请人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
发明人： Kazuo Tanaka , Hiroyuki Mizuno , Rie Nishiyama , Manabu Miyamoto
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H01L2924/0002 , H03K3/356104 , H01L2924/00
摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
摘要翻译：在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。在升高电路中，提供逻辑运算功能。

82. 发明授权

US08320703B2 Image processing method and apparatus 失效
标题翻译：图像处理方法和装置
公开(公告)号：US08320703B2
公开(公告)日：2012-11-27
申请号：US11945729
申请日：2007-11-27
申请人： Hiroyuki Mizuno
发明人： Hiroyuki Mizuno
IPC分类号： G06K9/40
CPC分类号： G06T5/006
摘要： An image processing method executes image processing to correct a non-uniform perceived resolution caused by image distortion correction, thereby achieving a uniform perceived resolution over an entire displayed image. The image processing method includes the step of adjusting an aperture compensation signal using distortion correcting data to correct a non-uniform perceived resolution caused in an image through partial conversion of magnification ratio by image distortion correction, thereby achieving a uniform perceived resolution.
摘要翻译：图像处理方法执行图像处理以校正由图像失真校正引起的不均匀的感知分辨率，从而在整个显示图像上实现均匀的感知分辨率。图像处理方法包括使用失真校正数据调整孔径补偿信号的步骤，以通过图像失真校正通过部分转换放大率来校正在图像中引起的不均匀的感觉分辨率，由此实现均匀的感知分辨率。

83. 发明授权

US07958379B2 Substrate bias switching unit for a low power processor 失效
标题翻译：用于低功耗处理器的基板偏置开关单元
公开(公告)号：US07958379B2
公开(公告)日：2011-06-07
申请号：US12346268
申请日：2008-12-30
申请人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , B23K11/24
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译：本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

84. 发明申请

US20110025409A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20110025409A1
公开(公告)日：2011-02-03
申请号：US12923681
申请日：2010-10-04
申请人： Hiroyuki Mizuno
发明人： Hiroyuki Mizuno
IPC分类号： G05F1/10
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3296 , H03K19/0016 , Y02D10/126 , Y02D10/172 , Y02D50/20 , Y10T307/25 , Y10T307/406
摘要： A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.
摘要翻译：一种用于快速和低功率操作的半导体集成电路器件，包括芯片的多个电路块，每个电路块具有不同功耗值的多个状态。功率管理电路通过考虑每个电路块的功耗和每个电路块中的每个状态转换来确定每个电路块的状态，以便不超过半导体集成电路器件的最大功耗值。最大功耗值可以在制造后预设或调节。

85. 发明申请

US20100053366A1 Device and method for image processing, program, and imaging apparatus 有权
标题翻译：用于图像处理，程序和成像装置的装置和方法
公开(公告)号：US20100053366A1
公开(公告)日：2010-03-04
申请号：US12461406
申请日：2009-08-11
申请人： Hiroyuki Mizuno , Satoshi Terada
发明人： Hiroyuki Mizuno , Satoshi Terada
IPC分类号： H04N9/73
CPC分类号： H04N9/735 , H04N5/144
摘要： An image processing device includes a white balancing unit configured to perform white balancing on an image signal within a pull-in frame defined by the color temperature of a light source to output the resultant signal, and a control unit configured to, when the white balancing unit performs white balancing on an image signal obtained by capturing an image of a subject illuminated by light emitted from a light emitting device, adjust a region of the pull-in frame on the basis of color information of a light emission signal output from the light emitting device.
摘要翻译：一种图像处理装置，包括白平衡单元，被配置为对由光源的色温定义的拉入框内的图像信号执行白平衡，以输出结果信号;以及控制单元，被配置为当白平衡通过拍摄由从发光装置发出的光照射的被摄体的图像而获得的图像信号进行白平衡，基于从光输出的发光信号的颜色信息来调整拉入框的区域发光装置。

86. 发明授权

US07560975B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07560975B2
公开(公告)日：2009-07-14
申请号：US11649766
申请日：2007-01-05
申请人： Kiyoo Itoh , Hiroyuki Mizuno
发明人： Kiyoo Itoh , Hiroyuki Mizuno
IPC分类号： H03K3/01
CPC分类号： G11C5/146 , G05F3/205 , G11C5/147 , H01L27/092 , H02M3/073 , H03K19/0013 , H03K19/0016 , H03K19/00315
摘要： The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.
摘要翻译：当电源接通时，在正常操作期间以及当电源电压被切断时，控制具有低阈值电压MOSFET的CMOS电路的阱电压。因此，CMOS电路可以以更低的功耗稳定地运行，因为当将电源电压施加到CMOS电路时或者当电源电压被切断时，由于锁存减小，并且在正常操作期间亚阈值电流减小。

87. 发明申请

US20090106541A1 PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION 有权
标题翻译：具有分支指令，电路，系统和制造和操作过程的处理器
公开(公告)号：US20090106541A1
公开(公告)日：2009-04-23
申请号：US12236674
申请日：2008-09-24
申请人： Hiroyuki Mizuno , Yoann Foucher
发明人： Hiroyuki Mizuno , Yoann Foucher
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3004 , G06F9/30058 , G06F9/30185 , G06F9/30189 , G06F9/3802 , G06F9/382 , G06F9/3844 , G06F9/3861
摘要： An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU) operable to select one of the selectable memory areas at a time, and an instruction fetch circuit (2520, 2550) operable to fetch a target instruction at an address from the selected one of the selectable memory areas. The processor includes an execution circuit (Pipeline) coupled to execute instructions from the instruction fetch circuit (2520, 2550) and operable to execute a first instruction for changing the selection by the memory area selection circuit (MMU) from a first one of the selectable memory areas to a second one of the selectable memory areas, the execution circuit (Pipeline) further operable to execute a branch instruction that points to a target instruction, access to the target instruction depending on actual change of selection to the second one of the memory areas; and the processor includes a logic circuit (3108, 3120, 3125, 3130, 3140) operable to ensure fetch of the target instruction in response to the branch instruction after actual change of selection. Other circuits, devices, systems, apparatus, and processes are also disclosed.
摘要翻译：电子处理器被提供用于具有可选存储区域的存储器（2530）。处理器包括一个存储区域选择电路（MMU），可操作以一次选择一个可选择的存储区域;以及指令提取电路（2520,2550），可操作以从所选择的一个可选择的存储区域中的一个地址获取目标指令记忆区域该处理器包括一个执行电路（管线），它被执行来执行来自指令提取电路（2520,2550）的指令，并可操作以执行一个第一指令，用于通过存储区域选择电路（MMU）从可选择的第一个存储器区域到可选存储区域中的第二个存储区域，执行电路（管道）还可操作以执行指向目标指令的转移指令，根据对存储器的第二存储器的选择的实际改变来访问目标指令地区并且处理器包括逻辑电路（3108,3120,3130,3130,3140），其可操作以在实际的选择改变之后响应于分支指令确保提取目标指令。还公开了其它电路，装置，系统，装置和方法。

88. 发明申请

US20090095711A1 MICROFABRICATION APPARATUS AND DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：微生物装置和装置制造方法
公开(公告)号：US20090095711A1
公开(公告)日：2009-04-16
申请号：US12237806
申请日：2008-09-25
申请人： Takeshi Koshiba , Yumi Nakajima , Tetsuro Nakasugi , Kazuo Tawarayama , Ikuo Yoneda , Hiroyuki Mizuno
发明人： Takeshi Koshiba , Yumi Nakajima , Tetsuro Nakasugi , Kazuo Tawarayama , Ikuo Yoneda , Hiroyuki Mizuno
IPC分类号： B44C1/22 , B29C43/02
CPC分类号： B29C43/021 , B29C33/303 , B29C43/003 , B29C43/58 , B29C2043/025 , B29C2043/142 , B29C2043/525 , B29C2043/5833 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F9/7003 , G03F9/7042 , G03F9/7088
摘要： A microfabrication apparatus for pressing an original plate including a pattern down on a substrate to transfer the pattern on the substrate includes a first measurement unit for measuring relative positional displacement between the substrate and the plate above the substrate, a position correction unit for correcting relative position between the substrate and the plate such that the pattern is to be transferred on a first predetermined position of the substrate based on the relative positional displacement measured by the first measurement unit, a pressing unit for pressing the plate above the substrate down on the substrate to transfer the pattern on the substrate in a state that the relative positional displacement between the substrate and the plate is corrected by the position correction unit, and a second measurement unit for measuring relative positional relationship between the pattern transferred on the substrate and a pattern previously formed on the substrate.
摘要翻译：一种用于将包括图案的原稿板压在基板上以将图案转印到基板上的微加工装置包括：第一测量单元，用于测量基板和基板上方的板之间的相对位置偏移;位置校正单元，用于校正相对位置在基板和板之间，基于由第一测量单元测量的相对位置位移，将图案转印到基板的第一预定位置上;按压单元，用于将基板上方的基板向下压在基板上，在通过位置校正单元校正基板和板之间的相对位置偏移的状态下，在基板上转印图案;以及第二测量单元，用于测量在基板上传送的图案与先前形成的图案之间的相对位置关系在基板上。

89. 发明申请

US20080136502A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20080136502A1
公开(公告)日：2008-06-12
申请号：US11987073
申请日：2007-11-27
申请人： Hiroyuki Mizuno , Koichiro Ishibashi , Takanori Shimura , Toshihiro Hattori
发明人： Hiroyuki Mizuno , Koichiro Ishibashi , Takanori Shimura , Toshihiro Hattori
IPC分类号： G05F3/16 , G05F3/02
CPC分类号： H01L27/0207 , G11C5/14 , G11C5/146 , G11C5/147 , H01L27/0928 , H01L27/11807 , H01L2924/0002 , H03K19/0016 , H01L2924/00
摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.
摘要翻译：为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括使用的开关晶体管（MN 1和MP 1）用于控制施加到衬底的电压，并且从衬底偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。

90. 发明授权

US07321252B2 Semiconductor integrated circuit 有权
公开(公告)号：US07321252B2
公开(公告)日：2008-01-22
申请号：US11396543
申请日：2006-04-04
申请人： Hiroyuki Mizuno , Koichiro Ishibashi , Takanori Shimura , Toshihiro Hattori
发明人： Hiroyuki Mizuno , Koichiro Ishibashi , Takanori Shimura , Toshihiro Hattori
IPC分类号： H03L5/00
CPC分类号： H01L27/0207 , G11C5/14 , G11C5/146 , G11C5/147 , H01L27/0928 , H01L27/11807 , H01L2924/0002 , H03K19/0016 , H01L2924/00
摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

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