专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07700461B2 Methods of laterally forming single crystalline thin film regions from seed layers 失效
标题翻译：从种子层横向形成单晶薄膜区域的方法
公开(公告)号：US07700461B2
公开(公告)日：2010-04-20
申请号：US12061253
申请日：2008-04-02
申请人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Pil-Kyu Kang
发明人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Pil-Kyu Kang
IPC分类号： H01L21/20
CPC分类号： H01L21/8221 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1285 , H01L29/78675
摘要： In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the substrate adjacent to the selection transistor. A seed layer including a single-crystalline material is formed in the opening. An amorphous thin film including an amorphous material is formed on the insulation layer pattern and the seed layer. The amorphous thin film is transformed into a single-crystalline thin film, using the single-crystalline material in the seed layer as a seed during a phase transition of the amorphous thin film, to form a channel layer on the insulation layer pattern and the seed layer. Therefore, the semiconductor device including the channel layer having the single-crystalline thin film may be manufactured.
摘要翻译：在制造半导体器件的方法中，包括在衬底上的选择晶体管和存储单元的串联结构。在衬底上形成绝缘层图案以覆盖串结构。绝缘层图案包括暴露基板的与选择晶体管相邻的部分的至少一个开口。在开口中形成包括单晶材料的晶种层。在绝缘层图案和种子层上形成包含非晶材料的非晶态薄膜。在非晶薄膜的相变期间，将晶种层中的单晶材料作为种子，将非晶薄膜转变为单晶薄膜，以在绝缘层图案和种子上形成沟道层层。因此，可以制造包括具有单晶薄膜的沟道层的半导体器件。

82. 发明授权

US07683405B2 MOS transistors having recesses with elevated source/drain regions 有权
标题翻译： MOS晶体管具有具有升高的源极/漏极区域的凹陷
公开(公告)号：US07683405B2
公开(公告)日：2010-03-23
申请号：US10886167
申请日：2004-07-07
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions and methods of fabricating the same are provided. The MOS transistors may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
摘要翻译：提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管及其制造方法。 MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。凹陷区域设置在与栅极图案相邻的衬底中。外凹层设置在凹陷区域的底表面上。在外延层中设置高浓度杂质区。凹陷区域可以使用化学干蚀刻技术形成。

83. 发明申请

US20090302377A1 VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20090302377A1
公开(公告)日：2009-12-10
申请号：US12478081
申请日：2009-06-04
申请人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
发明人： Yong-Hoon Son , Jong-Wook Lee , Jong-Hyuk Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/66666 , H01L29/7841
摘要： In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.
摘要翻译：在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案，单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

84. 发明申请

US20090142892A1 Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device 审中-公开
标题翻译：制造具有薄应变松弛缓冲图案的半导体器件及其相关器件的方法
公开(公告)号：US20090142892A1
公开(公告)日：2009-06-04
申请号：US11984538
申请日：2007-11-19
申请人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
发明人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823892 , H01L29/1054 , H01L29/4933 , H01L29/517
摘要： A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain.
摘要翻译：制造半导体器件的方法包括在衬底上形成缓冲图案，缓冲图案包括锗，使缓冲图案重结晶，形成应变弛豫缓冲图案，并在应变张弛缓冲图案上形成拉伸硅帽，在拉伸应变下。

85. 发明申请

US20080293224A1 METHOD OF FORMING A DIODE AND METHOD OF MANUFACTURING A PHASE-CHANGE MEMORY DEVICE USING THE SAME 审中-公开
标题翻译：二极管的制造方法和使用该二极管的相变存储器件的制造方法
公开(公告)号：US20080293224A1
公开(公告)日：2008-11-27
申请号：US12126120
申请日：2008-05-23
申请人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee
发明人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee
IPC分类号： H01L21/20
CPC分类号： H01L45/144 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： In a method of forming a diode, a first amorphous thin film doped with first impurities is formed on a single crystalline substrate. A second amorphous thin film doped with second impurities is formed on the first amorphous thin film. A laser beam having sufficient energy to melt both of the first and second amorphous thin films is irradiated on the first and second amorphous thin films to change crystal structures of the first and second amorphous thin films using the single crystalline substrate as a seed, so that first and second single crystalline thin films are sequentially formed on the single crystalline substrate.
摘要翻译：在形成二极管的方法中，在单晶衬底上形成掺杂有第一杂质的第一非晶薄膜。掺杂有第二杂质的第二非晶薄膜形成在第一非晶薄膜上。将具有足够的能量来熔化第一和第二非晶薄膜的激光束照射在第一和第二非晶薄膜上，以使用单晶基板作为种子来改变第一和第二非晶薄膜的晶体结构，从而使得第一和第二单晶薄膜依次形成在单晶衬底上。

86. 发明授权

US07432173B2 Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film 有权
标题翻译：制造具有激光成形单晶膜的绝缘体上硅衬底的方法
公开(公告)号：US07432173B2
公开(公告)日：2008-10-07
申请号：US11716894
申请日：2007-03-12
申请人： Sungkwan Kang , Yong-Hoon Son , Jongwook Lee , Yugyun Shin
发明人： Sungkwan Kang , Yong-Hoon Son , Jongwook Lee , Yugyun Shin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2026
摘要： In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor substrate with an opening that exposes a portion of the defined region of the semiconductor substrate having the single crystalline structure. A first non-single crystalline film is formed on the exposed portion of the semiconductor substrate and that at least substantially fills the opening in the first insulating film. A laser beam is generated that heats the first non-single crystalline film to change the first non-single crystalline film into a first single crystalline film having substantially the same single crystalline structure as the defined region of the semiconductor substrate.
摘要翻译：在制造绝缘体上硅衬底的一些方法中，提供在其至少其限定区域内包括单晶结构的半导体衬底。在半导体衬底的限定区域上形成第一绝缘膜，该开口具有露出具有单晶结构的半导体衬底的限定区域的一部分的开口。第一非单晶膜形成在半导体衬底的暴露部分上，并且至少基本上填充第一绝缘膜中的开口。产生激光束，其加热第一非单晶膜以将第一非单晶膜改变成具有与半导体衬底的限定区域基本上相同的单晶结构的第一单晶膜。

87. 发明授权

US07429504B2 Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
标题翻译：异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法
公开(公告)号：US07429504B2
公开(公告)日：2008-09-30
申请号：US11080737
申请日：2005-03-15
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/764 , H01L31/0336
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

88. 发明申请

US20080179665A1 Semiconductor Memory Devices and Methods of Forming the Same 审中-公开
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20080179665A1
公开(公告)日：2008-07-31
申请号：US12019046
申请日：2008-01-24
申请人： Jong-Wook Lee , Yong-Hoon Son , Si-Young Choi
发明人： Jong-Wook Lee , Yong-Hoon Son , Si-Young Choi
IPC分类号： H01L29/78
CPC分类号： H01L29/7841 , H01L21/268 , H01L27/0207 , H01L27/108 , H01L27/10802
摘要： A memory cell transistor includes a semiconductor substrate having a first impurity region of first conductivity type (e.g., N-type) therein. A U-shaped semiconductor layer having a second impurity region of first conductivity type therein is provided on the first impurity region. A gate insulating layer is provided, which lines a bottom and an inner sidewall of the U-shaped semiconductor layer. A gate electrode is provided on the gate insulating layer. The gate electrode is surrounded by the inner sidewall of the U-shaped semiconductor layer. A word line is provided, which is electrically coupled to the gate electrode, and a bit line is provided, which is electrically coupled to the second impurity region.
摘要翻译：存储单元晶体管包括其中具有第一导电类型的第一杂质区（例如N型）的半导体衬底。具有第一导电类型的第二杂质区的U形半导体层设置在第一杂质区上。提供了栅极绝缘层，其对U形半导体层的底部和内侧壁进行排列。栅电极设置在栅极绝缘层上。栅电极被U形半导体层的内侧壁包围。提供字线，其电耦合到栅电极，并且提供与第二杂质区电耦合的位线。

89. 发明授权

US07396761B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07396761B2
公开(公告)日：2008-07-08
申请号：US11605092
申请日：2006-11-28
申请人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
发明人： Sung-Kwan Kang , Jong-Wook Lee , Yong-Hoon Son , Yu-Gyun Shin , Jun-Ho Lee
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/44
CPC分类号： H01L29/66795 , H01L29/7851
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.
摘要翻译：在半导体器件和半导体器件的制造方法中，形成插头和沟道结构。塞子填充开口并且通道结构从插头向上延伸。通道结构具有基本垂直的侧壁。开口通过位于基板上的绝缘结构形成。塞子和通道结构包括通过激光束的照射从非晶状态改变的单晶状态的材料。通道结构掺杂有杂质如硼，磷或砷。

90. 发明授权

US07394117B2 Fin field effect transistors including epitaxial fins 有权
标题翻译： Fin场效应晶体管包括外延鳍片
公开(公告)号：US07394117B2
公开(公告)日：2008-07-01
申请号：US11622103
申请日：2007-01-11
申请人： In-Soo Jung , Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Yong-Hoon Son
发明人： In-Soo Jung , Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Yong-Hoon Son
IPC分类号： H01L29/34
CPC分类号： H01L29/7851 , H01L21/84 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/1203 , H01L29/66818 , H01L29/78603
摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.
摘要翻译：在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。翅片具有比有源区域的宽度窄的宽度。去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。在去除外延层的一部分之前，外延层可以原位掺杂。该方法还包括在鳍的顶表面和侧壁上形成导电层。还讨论了相关晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式