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81. 发明申请

US20060237706A1 Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory 失效
标题翻译：非挥发性半导体存储器和用于控制非易失性半导体存储器的方法
公开(公告)号：US20060237706A1
公开(公告)日：2006-10-26
申请号：US11396507
申请日：2006-04-05
申请人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
发明人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L47/00
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain-region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.
摘要翻译：一种包括多个存储单元晶体管的非易失性半导体存储器，所述多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

82. 发明申请

US20060186464A1 Nonvolatile semiconductor memory device having adjacent selection transistors connected together 有权
标题翻译：具有连接在一起的相邻选择晶体管的非易失性半导体存储器件
公开(公告)号：US20060186464A1
公开(公告)日：2006-08-24
申请号：US11407242
申请日：2006-04-20
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device comprising a semi-conductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate insulating film provided on the substrate, a source and drain provided in the substrate and aligned with the sides of the floating gate, an inter-gate insulating film provided on one side of the floating gate, and a control gate provided on the inter-gate insulating film and laying over the one side of the floating gate. The selection gates are connected by conductive members which are provided on the gate insulating film and embedded in the selection gates.
摘要翻译：一种半导体存储器件，包括半导体衬底，设置在衬底上的多个单元晶体管，设置在衬底上的多个选择栅极以及设置在单元晶体管之间和选择栅极之间的元件隔离区域。每个单元晶体管具有设置在设置在基板上的栅极绝缘膜上的浮置栅极，设置在基板中并与浮置栅极的侧对准的源极和漏极，设置在浮置栅极的一侧的栅极间绝缘膜以及设置在栅极间绝缘膜上并铺设在浮动栅极的一侧上的控制栅极。选择栅极由设置在栅极绝缘膜上并嵌入选择栅极的导电构件连接。

83. 发明授权

US07078813B2 Semiconductor device with double barrier film 失效
公开(公告)号：US07078813B2
公开(公告)日：2006-07-18
申请号：US11001223
申请日：2004-12-02
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

84. 发明授权

US07071511B2 Nonvolatile semiconductor memory device having adjacent selection transistors connected together 失效
公开(公告)号：US07071511B2
公开(公告)日：2006-07-04
申请号：US10988534
申请日：2004-11-16
申请人： Makoto Sakuma , Fumitaka Arai
发明人： Makoto Sakuma , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A semiconductor memory device comprising a semiconductor substrate, a plurality of cell transistors provided on the substrate, a plurality of selection gates provided on the substrate, and element-isolation regions provided between the cell transistors and between the selection gates. Each cell transistor has a floating gate provided on a gate insulating film provided on the substrate, a source and drain provided in the substrate and aligned with the sides of the floating gate, an inter-gate insulating film provided on one side of the floating gate, and a control gate provided on the inter-gate insulating film and laying over the one side of the floating gate. The selection gates are connected by conductive members which are provided on the gate insulating film and embedded in the selection gates.

85. 发明申请

US20060018181A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20060018181A1
公开(公告)日：2006-01-26
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

86. 发明申请

US20050253183A1 Non-volatile semiconductor memory device and method of fabricating the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20050253183A1
公开(公告)日：2005-11-17
申请号：US11091408
申请日：2005-03-29
申请人： Akira Umezawa , Fumitaka Arai
发明人： Akira Umezawa , Fumitaka Arai
IPC分类号： H01L29/417 , G11C16/04 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , G11C16/0416 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory device includes electrically rewritable memory cells formed in a cell array area of a semiconductor substrate. Each cell has spaced-apart source and drain regions, a charge storage layer overlying a channel between the source and drain, and a control gate overlying the charge storage layer. The device also includes a source line for common connection of the sources of those memory cells disposed along a word line by source-use conductors buried in mutually connected contact holes of the sources, drain-use conductors buried in contact holes of the drains of the cells, a transistor formed in a peripheral circuit area of the substrate to have a pair of source/drain regions and a gate electrode over a channel between the source/drain regions, and source/drain-use conductors buried in contact holes of the source/drain regions. Each source/drain buried conductor is longer than the drain-use buried conductor when viewing planarly.
摘要翻译：非易失性半导体存储器件包括形成在半导体衬底的单元阵列区域中的电可重写存储单元。每个单元具有间隔开的源极和漏极区域，覆盖源极和漏极之间的沟道的电荷存储层以及覆盖电荷存储层的控制栅极。该装置还包括源极线，用于通过埋在源极的相互连接的接触孔中的源极使用导体沿着字线设置的那些存储器单元的源的公共连接，埋入在源极的漏极的接触孔中的漏极使用导体形成在基板的外围电路区域中的晶体管，以在源极/漏极区域之间的沟道上方具有一对源极/漏极区域和栅电极，以及埋在源极的接触孔中的源极/漏极导体 /漏区。当平面观察时，每个源极/漏极掩埋导体比漏极使用的埋入导体长。

87. 发明授权

US06940752B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06940752B2
公开(公告)日：2005-09-06
申请号：US10920161
申请日：2004-08-18
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C7/00 , G11C11/56 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

88. 发明申请

US20050087795A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050087795A1
公开(公告)日：2005-04-28
申请号：US10940844
申请日：2004-09-15
申请人： Makoto Sakuma , Fumitaka Arai , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Yasuhiko Matsunaga
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42324 , H01L29/7881
摘要： Floating gates and control gates are alternately arranged on a substrate periodically in a first direction via a gate insulation film. Each floating gate has a first portion whose sectional shape is rectangular, and a second portion which is positioned substantially in a middle portion of the first portion and whose sectional shape is rectangular and whose length in a direction parallel to the first direction is smaller than that of the first portion. Each control gate has a third portion between the second portions of a pair of adjacent floating gates, and a fourth portion positioned between the first portions of a pair of adjacent floating gates. The floating gate and a pair of control gates positioned on opposite sides of the floating gate constitute one memory cell, the adjacent memory cells share the control gate positioned between the memory cells.
摘要翻译：浮栅和控制栅极经由栅极绝缘膜沿第一方向周期性地交替布置在基板上。每个浮动栅极具有截面形状为矩形的第一部分，并且第二部分基本上位于第一部分的中间部分中，并且其截面形状为矩形，并且其在与第一方向平行的方向上的长度小于的第一部分。每个控制栅极具有在一对相邻浮动栅极的第二部分之间的第三部分和位于一对相邻浮动栅极的第一部分之间的第四部分。位于浮动栅极相对侧的浮动栅极和一对控制栅极构成一个存储单元，相邻的存储单元共享位于存储单元之间的控制栅极。

89. 发明申请

US20050083744A1 Semiconductor memory device with MOS transistors each having a floating gate and a control gate 审中-公开
标题翻译：具有MOS晶体管的半导体存储器件，每个具有浮置栅极和控制栅极
公开(公告)号：US20050083744A1
公开(公告)日：2005-04-21
申请号：US10961880
申请日：2004-10-08
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor memory device includes a first MOS transistor, a second MOS transistor, and a sidewall insulating film. The first MOS transistor has a stacked gate and a silicide layer formed in a source and on the stacked gate. The second MOS transistor has a stacked gate and a silicide layer formed in a region and on the stacked gate. A drain of the first MOS transistor is connected to a source of the second MOS transistor. The sidewall insulating film is formed on the sidewall of the stacked gate of the first MOS transistor. The film thickness of the sidewall insulating film is greater than ½ of the distance between the stacked gates of the first and second MOS transistors. No silicide layer is formed in the drain of the first MOS transistor and in the source of the second MOS transistor.
摘要翻译：半导体存储器件包括第一MOS晶体管，第二MOS晶体管和侧壁绝缘膜。第一MOS晶体管具有形成在源极和堆叠栅极上的堆叠栅极和硅化物层。第二MOS晶体管具有形成在区域中和堆叠栅极上的堆叠栅极和硅化物层。第一MOS晶体管的漏极连接到第二MOS晶体管的源极。侧壁绝缘膜形成在第一MOS晶体管的堆叠栅极的侧壁上。侧壁绝缘膜的膜厚度大于第一和第二MOS晶体管的层叠栅极之间的距离的1/2。在第一MOS晶体管的漏极和第二MOS晶体管的源极中不形成硅化物层。

90. 发明授权

US06868010B2 Semiconductor memory device having row decoder in which high-voltage-applied portion is located adjacent to low-voltage-applied portion 失效
标题翻译：具有行解码器的半导体存储器件，其中高压施加部分位于与低电压施加部分相邻的位置
公开(公告)号：US06868010B2
公开(公告)日：2005-03-15
申请号：US10370512
申请日：2003-02-24
申请人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
发明人： Akira Shimizu , Riichiro Shirota , Fumitaka Arai
IPC分类号： G11C16/04 , G11C11/34 , G11C16/02 , G11C16/06 , G11C16/08 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/08 , G11C16/0483 , H01L27/105 , H01L27/115
摘要： A semiconductor memory device includes a first, second, and third memory cell transistors in which information can be electrically rewritten, addresses of which are consecutive in a row direction. One end of a current passage in each of a first, second, and third transfer transistors is connected to a control electrode of the first, second, and third memory cell transistors. A write voltage, a pass voltage lower than the write voltage, and a first voltage lower than the pass voltage are applied to the other ends of the first, second, and third transfer transistors. A first control section applies the first on-voltage to make the first transfer transistor conductive, to a gate of the first transfer transistor. A second control section applies a second on-voltage to make the second and third transfer transistors conductive, to gates of the second and third transfer transistors.
摘要翻译：半导体存储器件包括第一，第二和第三存储单元晶体管，其中信息可被电重写，其地址在行方向上是连续的。第一，第二和第三传输晶体管中的每一个中的电流通路的一端连接到第一，第二和第三存储单元晶体管的控制电极。写入电压，低于写入电压的通过电压以及低于通过电压的第一电压施加到第一，第二和第三转移晶体管的另一端。第一控制部分将第一传导晶体管导通的第一导通电压施加到第一传输晶体管的栅极。第二控制部分施加第二导通电压以使第二和第三转移晶体管导通到第二和第三转移晶体管的栅极。

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