专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07505312B2 Nonvolatile semiconductor memory device capable of controlling proximity effect due to coupling between adjacent charge storage layers 有权
标题翻译：能够通过相邻电荷存储层之间的耦合来控制邻近效应的非易失性半导体存储器件
公开(公告)号：US07505312B2
公开(公告)日：2009-03-17
申请号：US11447963
申请日：2006-06-07
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Atsuhiro Sato , Makoto Sakuma , Masato Endo , Kiyohito Nishihara , Keiji Shuto , Naohisa Iino
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/3427
摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.
摘要翻译：公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。

2. 发明申请

US20080054340A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING IMPROVED GATE ELECTRODE 失效
标题翻译：非线性半导体存储器件，包括改进的栅极电极
公开(公告)号：US20080054340A1
公开(公告)日：2008-03-06
申请号：US11877075
申请日：2007-10-23
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.
摘要翻译：通过栅极绝缘膜在半导体衬底上形成浮栅。扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

3. 发明授权

US07078813B2 Semiconductor device with double barrier film 失效
公开(公告)号：US07078813B2
公开(公告)日：2006-07-18
申请号：US11001223
申请日：2004-12-02
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

4. 发明申请

US20060018181A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20060018181A1
公开(公告)日：2006-01-26
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

5. 发明申请

US20050087795A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050087795A1
公开(公告)日：2005-04-28
申请号：US10940844
申请日：2004-09-15
申请人： Makoto Sakuma , Fumitaka Arai , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Yasuhiko Matsunaga
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42324 , H01L29/7881
摘要： Floating gates and control gates are alternately arranged on a substrate periodically in a first direction via a gate insulation film. Each floating gate has a first portion whose sectional shape is rectangular, and a second portion which is positioned substantially in a middle portion of the first portion and whose sectional shape is rectangular and whose length in a direction parallel to the first direction is smaller than that of the first portion. Each control gate has a third portion between the second portions of a pair of adjacent floating gates, and a fourth portion positioned between the first portions of a pair of adjacent floating gates. The floating gate and a pair of control gates positioned on opposite sides of the floating gate constitute one memory cell, the adjacent memory cells share the control gate positioned between the memory cells.
摘要翻译：浮栅和控制栅极经由栅极绝缘膜沿第一方向周期性地交替布置在基板上。每个浮动栅极具有截面形状为矩形的第一部分，并且第二部分基本上位于第一部分的中间部分中，并且其截面形状为矩形，并且其在与第一方向平行的方向上的长度小于的第一部分。每个控制栅极具有在一对相邻浮动栅极的第二部分之间的第三部分和位于一对相邻浮动栅极的第一部分之间的第四部分。位于浮动栅极相对侧的浮动栅极和一对控制栅极构成一个存储单元，相邻的存储单元共享位于存储单元之间的控制栅极。

6. 发明申请

US20050083744A1 Semiconductor memory device with MOS transistors each having a floating gate and a control gate 审中-公开
标题翻译：具有MOS晶体管的半导体存储器件，每个具有浮置栅极和控制栅极
公开(公告)号：US20050083744A1
公开(公告)日：2005-04-21
申请号：US10961880
申请日：2004-10-08
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , G11C16/0433 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor memory device includes a first MOS transistor, a second MOS transistor, and a sidewall insulating film. The first MOS transistor has a stacked gate and a silicide layer formed in a source and on the stacked gate. The second MOS transistor has a stacked gate and a silicide layer formed in a region and on the stacked gate. A drain of the first MOS transistor is connected to a source of the second MOS transistor. The sidewall insulating film is formed on the sidewall of the stacked gate of the first MOS transistor. The film thickness of the sidewall insulating film is greater than ½ of the distance between the stacked gates of the first and second MOS transistors. No silicide layer is formed in the drain of the first MOS transistor and in the source of the second MOS transistor.
摘要翻译：半导体存储器件包括第一MOS晶体管，第二MOS晶体管和侧壁绝缘膜。第一MOS晶体管具有形成在源极和堆叠栅极上的堆叠栅极和硅化物层。第二MOS晶体管具有形成在区域中和堆叠栅极上的堆叠栅极和硅化物层。第一MOS晶体管的漏极连接到第二MOS晶体管的源极。侧壁绝缘膜形成在第一MOS晶体管的堆叠栅极的侧壁上。侧壁绝缘膜的膜厚度大于第一和第二MOS晶体管的层叠栅极之间的距离的1/2。在第一MOS晶体管的漏极和第二MOS晶体管的源极中不形成硅化物层。

7. 发明申请

US20050018484A1 Nonvolatile semiconductor memory and programming method for the same 失效
标题翻译：非易失性半导体存储器和编程方法相同
公开(公告)号：US20050018484A1
公开(公告)日：2005-01-27
申请号：US10865937
申请日：2004-06-14
申请人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
发明人： Makoto Sakuma , Fumitaka Arai , Riichiro Shirota , Yasuhiko Matsunaga
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/34 , H01L27/10 , H01L29/78
CPC分类号： G11C16/10
摘要： A semiconductor memory has a memory cell matrix including a plurality of first and second cell columns alternately arranged along a row-direction, each of cell columns is implemented by a plurality of memory cell transistors, and peripheral circuits configured to drive the memory cell matrix and to read information from the memory cell matrix. The peripheral circuit encompasses (a) a leading program circuit configured to write first data into memory cell transistors in the first cell columns, (b) a lagging program circuit configured to write second data into memory cell transistors in the second cell columns after the first data are written, and (c) a voltage controller configured to control variation of threshold voltages for the memory cell transistors of the first cell columns.
摘要翻译：半导体存储器具有存储单元矩阵，其包括沿着行方向交替排列的多个第一和第二单元列，每个单元列由多个存储单元晶体管实现，并且外围电路被配置为驱动存储单元矩阵，从存储单元矩阵读取信息。外围电路包括（a）被配置为将第一数据写入第一单元列中的存储单元晶体管的引导程序电路，（b）滞后程序电路，被配置为将第二数据写入第一单元列之后的第二单元列中的存储单元晶体管写入数据，以及（c）被配置为控制第一单元列的存储单元晶体管的阈值电压的变化的电压控制器。

8. 发明授权

US07586786B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07586786B2
公开(公告)日：2009-09-08
申请号：US12106953
申请日：2008-04-21
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.
摘要翻译：一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

9. 发明授权

US07521749B2 Nonvolatile semiconductor memory device including improved gate electrode 失效
标题翻译：包括改进的栅电极的非易失性半导体存储器件
公开(公告)号：US07521749B2
公开(公告)日：2009-04-21
申请号：US11877075
申请日：2007-10-23
申请人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
发明人： Fumitaka Arai , Yasuhiko Matsunaga , Makoto Sakuma , Riichiro Shirota , Akira Shimizu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/10 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： A floating gate is formed on a semiconductor substrate via a gate insulating film. Diffused layers are formed as sources or drain regions on opposite sides of the floating gate in the semiconductor substrate. First and second control gates are formed opposite to both of the diffused layers on the opposite sides of the floating gate via an inter-gate insulating film to drive the floating gate.
摘要翻译：通过栅极绝缘膜在半导体衬底上形成浮栅。扩散层在半导体衬底中的浮置栅极的相对侧上形成为源区或漏极区。第一和第二控制栅极通过栅极间绝缘膜与浮动栅极的相对侧上的两个扩散层相对形成，以驱动浮置栅极。

10. 发明申请

US20080061357A1 Semiconductor device with double barrier film 审中-公开
标题翻译：具有双阻挡膜的半导体器件
公开(公告)号：US20080061357A1
公开(公告)日：2008-03-13
申请号：US11980561
申请日：2007-10-31
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式