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1. 发明申请

US20060018181A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20060018181A1
公开(公告)日：2006-01-26
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

2. 发明授权

US07586786B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07586786B2
公开(公告)日：2009-09-08
申请号：US12106953
申请日：2008-04-21
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.
摘要翻译：一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

3. 发明授权

US07382649B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07382649B2
公开(公告)日：2008-06-03
申请号：US11148336
申请日：2005-06-09
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C11/34
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
摘要翻译：非易失性半导体存储器包括存储单元单元，每个存储单元单元具有在列方向上排列的存储单元晶体管，并且能够写入和擦除电子数据; 以及布置在存储单元单元在列方向上串联连接的存储单元单元阵列的两侧的有源区上的触点，并且有源区上的触点由存储单元单元阵列共享; 其中，各个存储单元单元阵列的周期性移位长度等于或大于沿列方向排列的存储单元单元的周期长度的整数倍长度，以便与第相邻的存储单元单元阵列在行方向上排列。

4. 发明申请

US20090016108A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20090016108A1
公开(公告)日：2009-01-15
申请号：US12106953
申请日：2008-04-21
申请人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
发明人： Yasuhiko Matsunaga , Fumitaka Arai , Makoto Sakuma , Tadashi Iguchi , Hisashi Watanobe , Hiroaki Tsunoda
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： H01L27/0207 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage.
摘要翻译：一种从非易失性半导体存储器读出数据的方法，包括对位线接触施加第一电压的步骤; 向源极线接触施加第二电压，其中所述第二电压基本上小于所述第一电压; 施加第三和第四选择栅极晶体管的第三电压栅极，所述第三电压被配置为使所述第三和第四选择栅极晶体管导通; 对第二存储单元单元的多个存储单元晶体管的栅极施加第四电压，第四电压被配置为使第二存储单元单元的多个存储单元晶体管导通，取决于存储的数据在存储单元中; 对第一存储单元单元的多个存储单元晶体管的栅极施加第五电压，第五电压被配置为使第一存储单元单元的多个存储单元晶体管导通; 其中所述第五电压大于所述第四电压。

5. 发明申请

US20070293018A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：制备半导体器件的方法
公开(公告)号：US20070293018A1
公开(公告)日：2007-12-20
申请号：US11837915
申请日：2007-08-13
申请人： Ryuichi KAMO , Hisashi Watanobe , Tadashi Iguchi
发明人： Ryuichi KAMO , Hisashi Watanobe , Tadashi Iguchi
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521
摘要： In fabrication of a semiconductor device, a first insulating film, electrode film and silicon nitride film sequentially stacked on a semiconductor substrate are etched with the substrate so that a trench is formed. The electrode film is then exposed. A second insulating film buried in the trench is isotropically etched so that an upper side wall of the electrode film is exposed, so that a side end of an upper surface of the insulating film is located between the upper surfaces of the substrate and electrode film and so that a middle upper portion of an upper surface of the second insulating film is higher than the side end and lower than the upper surface of the first electrode film, A third insulating film is formed on the upper surface of the first electrode film so as to entirely cover the upper surface of the second insulating film.
摘要翻译：在半导体器件的制造中，用衬底蚀刻顺序层叠在半导体衬底上的第一绝缘膜，电极膜和氮化硅膜，从而形成沟槽。然后暴露电极膜。埋入沟槽中的第二绝缘膜被各向同性蚀刻，使得电极膜的上侧壁露出，使得绝缘膜的上表面的侧端位于基板和电极膜的上表面之间，使得第二绝缘膜的上表面的中间上部高于第一电极膜的侧端并且低于第一电极膜的上表面。在第一电极膜的上表面上形成第三绝缘膜，从而以完全覆盖第二绝缘膜的上表面。

6. 发明申请

US20050221578A1 Semiconductor device with shallow trench isolation and method of fabricating the same 失效
标题翻译：具有浅沟槽隔离的半导体器件及其制造方法
公开(公告)号：US20050221578A1
公开(公告)日：2005-10-06
申请号：US11060542
申请日：2005-02-18
申请人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
发明人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/00 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes a semiconductor substrate having an upper surface, a trench formed in the semiconductor substrate, a first insulating film formed on the semiconductor substrate so as to be located at opposite sides of the trench, a polycrystalline silicon film stacked on the first insulating film, the polycrystalline silicon film having an upper surface, a second insulating film buried in the trench and having an upper surface end located lower than the upper surface of the polycrystalline silicon film and higher than the upper surface of the semiconductor substrate, the second insulating film having a central upper surface located nearer to the upper surface of the polycrystalline silicon film than the upper surface end thereof.
摘要翻译：半导体器件包括具有上表面的半导体衬底，形成在半导体衬底中的沟槽，形成在半导体衬底上以便位于沟槽的相对侧的第一绝缘膜，堆叠在第一绝缘层上的多晶硅膜膜，具有上表面的多晶硅膜，埋在沟槽中的第二绝缘膜，具有位于比多晶硅膜的上表面低的上表面端，并且高于半导体衬底的上表面，第二绝缘体膜的中央上表面比其上表面端更靠近多晶硅膜的上表面。

7. 发明授权

US07276757B2 Semiconductor device with shallow trench isolation and method of fabricating the same 失效
标题翻译：具有浅沟槽隔离的半导体器件及其制造方法
公开(公告)号：US07276757B2
公开(公告)日：2007-10-02
申请号：US11060542
申请日：2005-02-18
申请人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
发明人： Ryuichi Kamo , Hisashi Watanobe , Tadashi Iguchi
IPC分类号： H01L29/788
CPC分类号： H01L21/76224 , H01L27/115 , H01L27/11521
摘要： A semiconductor device includes a semiconductor substrate including a first upper surface, a first insulating film including an upper portion including a first side wall having a first upper end and a second upper surface having a second upper end, a second insulating film formed on the first upper surface of the substrate, a floating gate electrode including a third upper surface, a second side wall and a lower surface, a third insulating film, and a control gate electrode. A height of the second upper end is lower than a height of the third upper surface and higher than a height of the first upper end relative to the first upper surface. The first upper end is located at a position higher than the lower surface of the floating gate electrode. The entire second side wall is aligned with the first side wall of the first insulating film.
摘要翻译：半导体器件包括：半导体衬底，包括第一上表面;第一绝缘膜，其包括上部，该上部包括具有第一上端的第一侧壁和具有第二上端的第二上表面;第二绝缘膜，基板的上表面，包括第三上表面，第二侧壁和下表面的浮栅，第三绝缘膜和控制栅电极。第二上端的高度低于第三上表面的高度，并且高于第一上端相对于第一上表面的高度。第一上端位于高于浮栅电极的下表面的位置。整个第二侧壁与第一绝缘膜的第一侧壁对齐。

8. 发明授权

US07535036B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07535036B2
公开(公告)日：2009-05-19
申请号：US11391319
申请日：2006-03-29
申请人： Hisashi Watanobe , Tooru Hara
发明人： Hisashi Watanobe , Tooru Hara
IPC分类号： H01L21/82
CPC分类号： H01L27/105 , H01L21/76804 , H01L21/76831 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose an interlayer insulating film, a plurality of connection wiring layers formed in a plurality of holes which are formed in the interlayer insulating film so as to extend through the conductive layers of each region, the connection wiring layers electrically connecting the conductive layers, and a spacer insulating film functioning as a spacer which is formed on inner sidewall surfaces of the holes and outer sidewall surfaces of the connection wiring layers in each region.
摘要翻译：半导体器件包括被划分为其中形成有存储单元的存储单元区域的半导体衬底和其中形成用于驱动存储单元的外围电路的外围电路区域，设置在每个区域中的多个导电层，以便插入层间绝缘膜，形成在多个孔中的多个连接布线层，所述多个孔形成在所述层间绝缘膜中，以贯穿各区域的导电层，所述连接布线层电连接所述导电层，间隔绝缘膜用作间隔件，其形成在每个区域中的连接布线层的孔的内侧壁表面和外侧壁表面上。

9. 发明申请

US20050236660A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050236660A1
公开(公告)日：2005-10-27
申请号：US11094466
申请日：2005-03-31
申请人： Hisashi Watanobe , Tooru Hara
发明人： Hisashi Watanobe , Tooru Hara
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/60 , H01L21/8242 , H01L21/8247 , H01L23/52 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76843 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L27/10888 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device comprising a lower conductive layer, an upper conductive layer located over the lower conductive layer, a first insulating film formed between upper and lower conductive layers, a plurality of connected wiring layers each of which has an upper surface, an upper side face and a sidewall outer periphery, each connected wiring layer being in structural contact with the upper conductive layer at the upper surface thereof and with the lower conductive layer, each connected wiring layer connecting the upper and lower conductive layers to each other, and a second insulating film formed on the sidewall outer periphery of each connected wiring layer so as to serve as a spacer between each connected wiring layer and the adjacent connected wiring layer, the second insulating film being made from a material differing from a material for the first insulating film. Each connected wiring layer is configured so as to be in structural contact with the upper conductive layer at the upper surface and upper side face of each connected wiring layer.
摘要翻译：一种半导体器件，包括下导电层，位于下导电层上的上导电层，形成在上导电层和下导电层之间的第一绝缘膜，多个连接布线层，每个具有上表面，上侧面和侧壁外周，每个连接的布线层在其上表面与上导电层结构接触，并具有下导电层，每个连接的布线层将上导电层和下导电层彼此连接，第二绝缘层形成在每个连接的布线层的侧壁外周上，以便在每个连接的布线层和相邻的连接的布线层之间用作间隔物，第二绝缘膜由与第一绝缘膜的材料不同的材料制成。每个连接的布线层被配置为在每个连接的布线层的上表面和上侧面处与上导电层结构接触。

10. 发明授权

US07511330B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07511330B2
公开(公告)日：2009-03-31
申请号：US11094466
申请日：2005-03-31
申请人： Hisashi Watanobe , Tooru Hara
发明人： Hisashi Watanobe , Tooru Hara
IPC分类号： H01L21/76 , H01L29/76
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76843 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L27/10888 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a semiconductor substrate, a gate insulating film, gate electrodes, a first silicon oxide film, bit lines formed on the first silicon oxide film and including lower surfaces having respective recesses, a contact plug layer located between the gate electrodes and including a first portion, a second portion having a fourth side surface between the opposed second side surfaces of first silicon oxide film and a third portion having an upper surface and fifth side surfaces embedded in the respective recesses of the bit line, a first silicon nitride layer between a third side surface of the first portion of the contact plug and a first side surface of the gate electrode, and a second silicon oxide film. The entire upper surface and fifth side surface of the third portion of the contact plug directly contact with inner surfaces of the recesses respectively.
摘要翻译：半导体器件包括半导体衬底，栅极绝缘膜，栅电极，第一氧化硅膜，形成在第一氧化硅膜上的位线，并且包括具有各自凹部的下表面;位于栅电极之间的接触塞层，第一部分，第二部分，其具有在第一氧化硅膜的相对的第二侧表面之间的第四侧表面和具有上表面的第三部分和嵌入位线的各个凹部中的第五侧表面;第一氮化硅层在所述接触插塞的第一部分的第三侧表面和所述栅电极的第一侧表面之间和第二氧化硅膜之间。接触插塞的第三部分的整个上表面和第五侧表面分别直接与凹槽的内表面接触。

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