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    • 89. 发明公开
    • UTILIZING PIPELINE REGISTERS AS INTERMEDIATE STORAGE
    • VERWENDUNG VON PIPELINERISISN ALS ZWISCHENSPEICHER
    • EP3143495A1
    • 2017-03-22
    • EP15724805.5
    • 2015-04-21
    • Qualcomm Incorporated
    • CHEN, LinDU, YunUDAYAKUMARAN, SumeshZHANG, ChihongGRUBER, Andrew Evan
    • G06F9/30G06F9/38
    • G06F9/3012G06F9/30032G06F9/3017G06F9/3869G06F9/3875
    • In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.
    • 在一个示例中,一种方法包括响应于由处理单元接收请求将第一值从第一通用寄存器(GPR)移动到第三GPR的一个或多个指令,并且第二值从第二个 GPR到第四个GPR,由初始逻辑单元和在第一时钟周期期间将第一个值复制到初始流水线寄存器,通过初始逻辑复制第二个时钟周期,将第二个值复制到初始流水线寄存器 ,由最终逻辑单元和在第三时钟周期期间将第一值从最终流水线寄存器复制到第三GPR,并且由最终逻辑单元和在第四时钟周期期间复制来自最终流水线的第二值 注册到第四个GPR。