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1. 发明申请

WO2009132013A1 PROGRAMMABLE STREAMING PROCESSOR WITH MIXED PRECISION INSTRUCTION EXECUTION 审中-公开
标题翻译：具有混合精度指令执行的可编程流水处理器
公开(公告)号：WO2009132013A1
公开(公告)日：2009-10-29
申请号：PCT/US2009/041268
申请日：2009-04-21
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , JIAO, Guofang , MOLLOY, Stephen
发明人： DU, Yun , YU, Chun , JIAO, Guofang , MOLLOY, Stephen
IPC分类号： G06T15/00 , G06F1/32
CPC分类号： G06T15/005 , G06F8/47
摘要： The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision. The controller then causes the selected execution unit to execute the instruction with the indicated data precision using the graphics data associated with the instruction.
摘要翻译：本公开涉及一种能够使用不同的执行单元执行混合精度（例如，全精度，半精度）指令的可编程流处理器。各种执行单元都能够使用图形数据来执行特定精度级别的指令。示例性可编程着色器处理器包括控制器和多个执行单元。控制器被配置为接收用于执行的指令并且接收用于执行指令的数据精度的指示。控制器还被配置为接收单独的转换指令，该指令在执行时将与指令相关联的图形数据转换为所指示的数据精度。当可操作时，控制器基于指示的数据精度选择一个执行单元。然后，控制器使所选择的执行单元使用与指令相关联的图形数据，以指示的数据精度执行指令。

2. 发明申请

WO2008103750A2 DYNAMIC CONFIGURABLE TEXTURE CACHE FOR MULTI-TEXTURING 审中-公开
标题翻译：动态可配置纹理高速缓存用于多种纹理
公开(公告)号：WO2008103750A2
公开(公告)日：2008-08-28
申请号：PCT/US2008/054452
申请日：2008-02-20
申请人： QUALCOMM Incorporated , YU, Chun
发明人： YU, Chun
CPC分类号： G06F12/0846 , G06F12/0864 , G06F12/0875 , G06F2212/601
摘要： Techniques for dynamically configuring a texture cache are disclosed. During a texture mapping process of a three-dimensional (3D) graphics pipeline, if the batch is for single texture mapping, the texture cache is configured as a n-way set-associative texture cache. However, if the batch is for multi-texture mapping the n-way set-associated texture cache is divided into at n/M-way set-associative sub-caches where n and M are integers greater than 1 and n is divisible by M.
摘要翻译：公开了动态配置纹理缓存的技术。在三维（3D）图形流水线的纹理映射过程中，如果批处理是单纹理映射，则将纹理缓存配置为n路集关联纹理缓存。然而，如果批处理是用于多纹理映射的，那么将n路集相关的纹理缓存划分为n / M路集相关子缓存，其中n和M是大于1的整数且n可被M整除

3. 发明申请

WO2008039950A1 GRAPHICS PROCESSING UNIT WITH UNIFIED VERTEX CACHE AND SHADER REGISTER FILE 审中-公开
标题翻译：具有统一VERTEX CACHE和SHADER寄存器文件的图形处理单元
公开(公告)号：WO2008039950A1
公开(公告)日：2008-04-03
申请号：PCT/US2007/079784
申请日：2007-09-27
申请人： QUALCOMM Incorporated , JIAO, Guofang , YU, Chun , DU, Yun
发明人： JIAO, Guofang , YU, Chun , DU, Yun
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.
摘要翻译：描述了使用统一的顶点高速缓存和着色器寄存器文件处理具有图形处理单元（GPU）的计算机化图像的技术。这些技术包括创建耦合到GPU流水线的共享着色器和耦合到共享着色器的统一顶点高速缓存和着色器寄存器文件，以基本上消除GPU流水线内的数据移动。 GPU管道将基于图像的图像几何的图像几何信息发送到共享着色器。共享着色器执行顶点着色以生成图像中顶点坐标和顶点属性。共享着色器然后将顶点属性存储在统一的顶点缓存和着色器寄存器文件中，并且仅将顶点的顶点坐标发送回GPU管道。 GPU流水线基于顶点坐标处理图像，共享着色器基于顶点属性处理图像。

4. 发明申请

WO2007149979A2 UNIFIED VIRTUAL ADDRESSED REGISTER FILE 审中-公开
标题翻译：统一的虚拟寻址寄存器文件
公开(公告)号：WO2007149979A2
公开(公告)日：2007-12-27
申请号：PCT/US2007/071775
申请日：2007-06-21
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , HSU, De,D. , JIAO, Golf
发明人： DU, Yun , YU, Chun , HSU, De,D. , JIAO, Golf
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/30138 , G06F9/384 , G06T15/005
摘要： A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.
摘要翻译：提供了多线程处理器，例如着色器处理器，具有由多个线程共享的内部统一存储器空间，并且根据需要动态分配给线程。映射表将虚拟寄存器映射到统一存储空间中的可用内部地址，以便线程寄存器可以存储在连续或不连续的存储器地址中。虚拟寄存器的动态大小允许根据线程寄存器中数据的类型和大小灵活分配统一存储空间。另一个特征提供了用于将统计存储器空间中的图形数据存储以改善从存储器空间获取和存储操作的有效方法。特别地，线程中的四个像素的像素数据被存储在具有独立输入/输出端口的四个存储器件中，这些存储器件允许以单个时钟周期读取四个像素进行处理。

5. 发明申请

WO2007140338A2 GRAPHICS PROCESSOR WITH ARITHMETIC AND ELEMENTARY FUNCTION UNITS 审中-公开
标题翻译：具有算术和元素功能单元的图形处理器
公开(公告)号：WO2007140338A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069803
申请日：2007-05-25
申请人： QUALCOMM Incorporated , BOURD, Alexei, V. , DU, Yun , YU, Chun , JIAO, Guofang
发明人： BOURD, Alexei, V. , DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F9/38
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.
摘要翻译：描述能够有效执行算术运算和计算基本功能的图形处理器。图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。单个基本功能单元可以一次操作一个像素的一个分量。使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

6. 发明申请

WO2005086090A3 GRAPHICS PIPELINE AND METHOD HAVING EARLY DEPTH DETECTION 审中-公开
公开(公告)号：WO2005086090A3
公开(公告)日：2005-09-15
申请号：PCT/US2005/007158
申请日：2005-03-02
申请人： QUALCOMM INCORPORATED , ANDERSON, Michael Hugh , IRVINE, Ann Chris , KAMATH, Nidish Ramachandra , YU, Chun , CHUANG, Dan Minglun , TIAN, Yushi , QI, Yingyong
发明人： ANDERSON, Michael Hugh , IRVINE, Ann Chris , KAMATH, Nidish Ramachandra , YU, Chun , CHUANG, Dan Minglun , TIAN, Yushi , QI, Yingyong
IPC分类号： G06T15/00
摘要： A graphics pipeline includes a plurality of sequentially arranged processing stages which render display pixel data from input primitive object data. The processing stages include at least a texturing stage and a depth test stage, and the depth test stage may be located earlier in the graphics pipeline than the texturing stage.

7. 发明申请

WO2021151248A1 METHODS AND APPARATUS TO FACILITATE DEDICATED BINDLESS STATE PROCESSOR 审中-公开
公开(公告)号：WO2021151248A1
公开(公告)日：2021-08-05
申请号：PCT/CN2020/074108
申请日：2020-01-31
申请人： QUALCOMM INCORPORATED
发明人： DU, Yun , GRUBER, Andrew Evan , YU, Chun , ZHANG, Chihong , FRISINGER, Thomas Edwin , HAMMERSTONE, Richard , YING, Zilin , QI, Heng , XU, Quanquan , GU, Sheng
IPC分类号： G06T1/60
摘要： Disclosure relates to methods and apparatus for graphics processing. Techniques facilitate improves bindless state processing at a graphics processor. At a graphics processor, a shader program including a preamble section and a main instructions section can be received. With a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program can be executed. The main instructions section and the constant data to a streaming processor for executing the shader program can be distributed.

8. 发明申请

WO2014085002A1 MEMORY MANAGEMENT USING DYNAMICALLY ALLOCATED DIRTY MASK SPACE 审中-公开
标题翻译：使用动态分配的真皮掩蔽空间进行记忆管理
公开(公告)号：WO2014085002A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/067111
申请日：2013-10-28
申请人： QUALCOMM INCORPORATED
发明人： LIANG, Jian , YU, Chun , XU, Fei
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0886 , G06F12/0895 , G06F2212/604
摘要： Systems and methods related to a memory system including a cache memory are disclosed. The cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated.
摘要翻译：公开了与包括高速缓冲存储器的存储器系统有关的系统和方法。高速缓冲存储器系统包括包括多个高速缓存存储器线的高速缓存存储器和包括多个脏掩模的脏缓冲器。高速缓存控制器被配置为当对相应高速缓存存储器线的写入不是对该高速缓存存储器线的完全写入时，将一个脏掩模分配给每个高速缓存存储器线。每个脏屏蔽指示一个缓存存储器线中的数据单元的脏状态。高速缓存控制器存储将脏屏蔽与分配有脏屏蔽的高速缓冲存储器线相关联的标识（ID）信息。

9. 发明申请

WO2009049255A3 DEMAND-BASED POWER CONTROL IN A GRAPHICS PROCESSING UNIT 审中-公开
公开(公告)号：WO2009049255A3
公开(公告)日：2009-04-16
申请号：PCT/US2008/079644
申请日：2008-10-10
申请人： QUALCOMM INCORPORATED , DU, Yun , YU, Chun , JIAO, Guofang
发明人： DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F1/32 , G06F9/38
摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.

10. 发明申请

WO2008128097A2 PROGRAMMABLE GRAPHICS PROCESSING ELEMENT 审中-公开
标题翻译：可编程图形处理元件
公开(公告)号：WO2008128097A2
公开(公告)日：2008-10-23
申请号：PCT/US2008/060103
申请日：2008-04-11
申请人： QUALCOMM INCORPORATED , JIAO, Guofang , CHEN, Lingjun Frank , YU, Chun , DU, Yun
发明人： JIAO, Guofang , CHEN, Lingjun Frank , YU, Chun , DU, Yun
IPC分类号： G06T15/00 , G06F13/10 , G06T15/40 , G06T15/50
CPC分类号： G06T15/005 , G06T15/40 , G06T15/503
摘要： In general, this disclosure describes techniques for performing graphics operations using programmable processing units in a graphics processing unit (GPU). As described herein, a GPU includes a graphics pipeline that includes a programmable graphics processing element (PGPE). In accordance with the techniques described herein, an arbitrary set of instructions is loaded into the PGPE. Subsequently, the PGPE may execute the set of instructions in order to generate a new pixel object. A pixel object describes a displayable pixel. The new pixel object may represent a result of performing a graphics operation on a first pixel object. A display device may display a pixel described by the new pixel object.
摘要翻译：通常，本公开描述了使用图形处理单元（GPU）中的可编程处理单元执行图形操作的技术。如本文所述，GPU包括包括可编程图形处理元件（PGPE）的图形流水线。根据本文描述的技术，任意一组指令被加载到PGPE中。随后，PGPE可以执行该组指令以便生成新的像素对象。像素对象描述可显示像素。新的像素对象可以表示对第一像素对象执行图形操作的结果。显示装置可以显示由新像素对象描述的像素。

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