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1. 发明申请

WO2023043573A1 FOVEATED BINNED RENDERING ASSOCIATED WITH SAMPLE SPACES 审中-公开
公开(公告)号：WO2023043573A1
公开(公告)日：2023-03-23
申请号：PCT/US2022/040952
申请日：2022-08-19
申请人： QUALCOMM INCORPORATED
发明人： NEELAMBARAN, Ashokanand , GUPTA, Piyush , BHIRAVABHATLA, Kalyan, Kumar , WANG, Tao , GRUBER, Andrew, Evan
IPC分类号： G06T11/40
摘要： Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with an upscaled sample space and/or a downscaled sample space. The apparatus may also perform a binning pass for the plurality of primitives, the binning pass being associated with an unscaled sample space, where the binning pass sorts each of the primitives into one or more bins associated with each of the one or more frames. Further, the apparatus may perform one of one or more rendering passes for each of the one or more bins. The apparatus may also rasterize each of the plurality of primitives based on at least one of the upscaled sample space or the downscaled sample space.

2. 发明申请

WO2017014838A1 ZERO PIXEL CULLING FOR GRAPHICS PROCESSING 审中-公开
标题翻译： ZERO PIXEL CULLING FOR GRAPHICAL PROCESSING
公开(公告)号：WO2017014838A1
公开(公告)日：2017-01-26
申请号：PCT/US2016/034456
申请日：2016-05-26
申请人： QUALCOMM INCORPORATED
发明人： DUVVURU, Nagarjuna , WANG, Tao , LIANG, Jian , WANG, Chunlin
IPC分类号： G06T15/40 , G06T11/40
CPC分类号： G06T15/40 , G06T11/40 , G06T15/005 , G06T2200/04 , G06T2200/12 , G06T2200/28
摘要： A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.
摘要翻译：图形处理单元（GPU）可以包括被配置为确定三角形的坐标的三角形设置引擎（TSE），基于角度旋转三角形的坐标。为了旋转坐标，TSE在旋转的域中生成三角形的坐标，并根据旋转域中的三角形的坐标确定旋转域中边界框的坐标。 TSE确定旋转域中的第一多个平行扫描线和旋转域中的第二多个并行扫描线。第一和第二扫描线是垂直的。 TSE确定边界框坐标是否位于两个相邻的扫描线之内。如果边界框坐标位于两个相邻的扫描线内，则TSE会从场景中删除三角形。

3. 发明申请

WO2015123029A1 TECHNIQUES FOR CONSERVATIVE RASTERIZATION 审中-公开
标题翻译：保守放电技术
公开(公告)号：WO2015123029A1
公开(公告)日：2015-08-20
申请号：PCT/US2015/013550
申请日：2015-01-29
申请人： QUALCOMM INCORPORATED
发明人： MOURI, Ouns , GOEL, Vineet , WANG, Tao
IPC分类号： G06T11/40
CPC分类号： G06T1/20 , G06T11/40 , G06T17/10 , G09G5/18 , G09G2310/08
摘要： This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.
摘要翻译：本公开描述了一种用于在处理器中执行保守光栅化的方法，包括通过基于所确定的顶点确定一组边缘方程来确定原语的边缘来定义基元的边缘，其中边缘方程基于边缘移位参数加上使用所确定的边缘方程来确定触摸图元的边缘的像素，以及使用所确定的像素来对原图进行光栅化。

4. 发明申请

WO2023287541A1 OPTIMIZATION OF DEPTH AND SHADOW PASS RENDERING IN TILE BASED ARCHITECTURES 审中-公开
公开(公告)号：WO2023287541A1
公开(公告)日：2023-01-19
申请号：PCT/US2022/033546
申请日：2022-06-15
申请人： QUALCOMM INCORPORATED
发明人： KURUMANGHAT, Sreyas , BHIRAVABHATLA, Kalyan Kumar , GRUBER, Andrew Evan , WANG, Tao , YANG, Baoguang , AKKARAJU, Pavan Kumar
IPC分类号： G06T15/00 , G06T15/40
摘要： The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.

5. 发明申请

WO2017146822A1 SINGLE PASS BOUNDING VOLUME HIERARCHY RASTERIZATION 审中-公开
标题翻译：单通约束容积等级脆弱性
公开(公告)号：WO2017146822A1
公开(公告)日：2017-08-31
申请号：PCT/US2017/012307
申请日：2017-01-05
申请人： QUALCOMM INCORPORATED
发明人： OBERT, Juraj , WANG, Tao , GOEL, Vineet
IPC分类号： G06T15/06
CPC分类号： G06T15/005 , G06T15/06 , G06T2200/28 , G06T2210/21
摘要： A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
摘要翻译：在至少一个处理器上运行的渲染输出单元可以接收要写入渲染目标中的像素位置的源像素值，其中源像素值与层级中的源节点相关联结构体。渲染输出单元可以接收渲染目标中的像素位置的目标像素值，其中目标像素值与分层结构中的目的地节点相关联。呈现输出单元可以确定分层结构中的源节点和目的地节点的最低公共祖先节点。渲染输出单元可将与源节点和目的地节点的最低公共祖先节点相关联的结果像素值输出到渲染目标中的像素位置。

6. 发明申请

WO2017139069A1 SYSTEM AND METHOD FOR MULTI-TILE DATA TRANSACTIONS IN A SYSTEM ON A CHIP 审中-公开
标题翻译：用于在芯片上的系统中进行多层数据交换的系统和方法
公开(公告)号：WO2017139069A1
公开(公告)日：2017-08-17
申请号：PCT/US2017/013599
申请日：2017-01-14
申请人： QUALCOMM INCORPORATED
发明人： GADELRAB, Serag , VARIA, Meghal , WURJANTARA, Wisnu , SUNG, Clara Ka Wah , STERNBERG, Mark , ANDRIJANIC, Vladan , RINALDI, Antonio , CHAMARTY, Vinod , SINHA, Pooja , WANG, Tao , GRUBER, Andrew
IPC分类号： G06F13/16
CPC分类号： G06F9/467 , G06F13/1668 , G06F15/7807 , G06F17/30153 , G06F2212/401 , H03M7/30
摘要： Various embodiments of methods and systems for managing compressed data transaction sizes in a system on a chip ("SoC") in a portable computing device ("PCD") are disclosed. Based on lengths of compressed data tiles associated in a group, wherein the compressed data tiles are comprised within a compressed image file, multiple compressed data tiles may be aggregated into a single, multi-tile transaction. A metadata file may be generated in association with the single multi-tile transaction to identify the transaction as a multi-tile transaction and provide offset data to distinguish data associated with the compressed data tiles. Using the metadata, embodiments of the solution may provide for random access and modification of the compressed data stored in association with a multi-tile transaction.
摘要翻译：公开了用于管理便携式计算设备（“PCD”）中的片上系统（“SoC”）中的压缩数据事务大小的方法和系统的各种实施例。基于组中关联的压缩数据瓦片的长度，其中压缩数据瓦片包含在压缩图像文件内，多个压缩数据瓦片可以被聚合成单个多瓦片事务。元数据文件可以与单个多瓦片事务相关联地生成以将事务识别为多瓦片事务并且提供偏移数据以区分与压缩的数据瓦片相关联的数据。使用元数据，解决方案的实施例可以提供对与多瓦片事务相关联地存储的压缩数据的随机访问和修改。

7. 发明申请

WO2017023408A1 SYSTEMS, METHODS, AND APPARATUS FOR FREQUENCY RESET OF A MEMORY 审中-公开
标题翻译：用于存储器频率重置的系统，方法和装置
公开(公告)号：WO2017023408A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/035520
申请日：2016-06-02
申请人： QUALCOMM INCORPORATED
发明人： JOSE, Edwin , WANG, Tao
IPC分类号： G06F13/16
CPC分类号： G06F11/1471 , G06F3/0619 , G06F3/0632 , G06F3/0679 , G06F13/1668 , G06F2201/805 , G06F2201/84 , G06F2201/85
摘要： Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.
摘要翻译：本公开的一些方面包括用于诸如DRAM的存储器的自刷新入口序列，其可以用于避免系统处理器和系统存储器之间的频率不匹配。自刷新入口序列可能会在存储器中发信号通知复位频率设定点状态，并在自刷新过程退出时默认为上电状态。另一方面，可以使用新的模式寄存器来指示频率设定点需要在下一个自刷新输入命令之后复位。在这方面，处理器将执行模式寄存器写入命令，随后响应于碰撞事件的发生而进行自刷新条目。然后，在自刷新输入执行结束时，存储器将重置为默认频率设定点。

8. 发明申请

WO2022095010A1 METHODS AND APPARATUS FOR RASTERIZATION OF COMPUTE WORKLOADS 审中-公开
公开(公告)号：WO2022095010A1
公开(公告)日：2022-05-12
申请号：PCT/CN2020/127436
申请日：2020-11-09
申请人： QUALCOMM INCORPORATED , ZHANG, Yibin , YING, Zilin , DU, Yun , QI, Heng , YU, Jiexia , YU, Yang , GRUBER, Andrew, Evan , LIANG, Jian , WANG, Tao , BOURD, Alexei Vladimirovich , ZHONG, Gang , HUANG, Minjie
发明人： ZHANG, Yibin , YING, Zilin , DU, Yun , QI, Heng , YU, Jiexia , YU, Yang , GRUBER, Andrew, Evan , LIANG, Jian , WANG, Tao , BOURD, Alexei Vladimirovich , ZHONG, Gang , HUANG, Minjie
IPC分类号： G06T1/00
摘要： The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.

9. 发明申请

WO2021091643A1 METHODS AND APPARATUS FOR REDUCING THE TRANSFER OF RENDERING INFORMATION 审中-公开
公开(公告)号：WO2021091643A1
公开(公告)日：2021-05-14
申请号：PCT/US2020/054576
申请日：2020-10-07
申请人： QUALCOMM INCORPORATED
发明人： WANG, Tao , KHANDELWAL, Shambhoo , GRUBER, Andrew Evan , YU, Shangmei , GAO, Jing , SHAO, Junmei , FRISINGER, Thomas Edwin , HAMMERSTONE, Rick
IPC分类号： G06T1/20 , G06T15/00
摘要： The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

10. 发明申请

WO2018111402A1 FETCH REDUCTION FOR FIXED COLOR AND PATTERN SUB-FRAMES 审中-公开
公开(公告)号：WO2018111402A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/057637
申请日：2017-10-20
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Andrew Evan , GADELRAB, Serag , MA, Zhenbiao , VARIA, Meghal , WANG, Tao , LONGO, Tom , STERNBERG, Mark , CHOW, Paul
IPC分类号： G09G5/36 , G09G5/395 , G06T11/40
摘要： Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.

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