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81. 发明授权

US07115996B2 Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped 有权
公开(公告)号：US07115996B2
公开(公告)日：2006-10-03
申请号：US10852142
申请日：2004-05-25
申请人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
发明人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/2885 , H01L21/76856 , H01L21/76858 , H01L21/76862 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05546 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/15747 , H05K3/244 , H01L2924/00
摘要： A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed.

82. 发明授权

US06992390B2 Liner with improved electromigration redundancy for damascene interconnects 失效
标题翻译：具有改进的大马士革互连的电迁移冗余的衬垫
公开(公告)号：US06992390B2
公开(公告)日：2006-01-31
申请号：US10702651
申请日：2003-11-07
申请人： Daniel C. Edelstein , Baozhen Li , Timothy D. Sullivan
发明人： Daniel C. Edelstein , Baozhen Li , Timothy D. Sullivan
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure for semiconductor integrated circuits is disclosed. The interconnection structure comprises a redundant layer, and at least one adhesion/diffusion barrier layer. The redundant layer comprises a metal or metal alloy selected from Ta, Mo, W, Be, Cr, Co, Ir, Ni, Nb, Os, Pd, Pt, Rb, Rh, Ru, and Th.
摘要翻译：公开了一种用于半导体集成电路的互连结构。互连结构包括冗余层和至少一个粘附/扩散阻挡层。冗余层包括选自Ta，Mo，W，Be，Cr，Co，Ir，Ni，Nb，Os，Pd，Pt，Rb，Rh，Ru和Th中的金属或金属合金。

83. 发明授权

US06784088B2 Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped 有权
标题翻译：选择性地与铟或锡青铜和/或其氧化物覆盖互连的方法以及如此封闭的互连
公开(公告)号：US06784088B2
公开(公告)日：2004-08-31
申请号：US10345288
申请日：2003-01-16
申请人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
发明人： Daniel C. Edelstein , Sung Kwon Kang , Maurice McGlashan-Powell , Eugene J. O'Sullivan , George F. Walker
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/2885 , H01L21/76856 , H01L21/76858 , H01L21/76862 , H01L23/53238 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05546 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/15747 , H05K3/244 , H01L2924/00
摘要： A method to selectively cap a cooper BEOL terminal pad with a Cu/Sn/Au alloy. The method includes providing one or more Cu BEOL terminal pads and coating the pads with a Sn coating followed by coating the Sn with a Au coating. The coated pads are then annealed to form the Cu/Sn/Au capping alloy.
摘要翻译：一种用Cu / Sn / Au合金选择性地覆盖铜合金BEOL端子焊盘的方法。该方法包括提供一个或多个Cu BEOL端子焊盘并且用焊锡涂覆Sn涂层，然后用Au涂层涂覆Sn。然后将涂覆的焊盘退火以形成Cu / Sn / Au封盖合金。

84. 发明授权

US06746947B2 Post-fuse blow corrosion prevention structure for copper fuses 有权
标题翻译：铜熔丝保险丝熔断防腐结构
公开(公告)号：US06746947B2
公开(公告)日：2004-06-08
申请号：US10254277
申请日：2002-09-25
申请人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
发明人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76843 , H01L23/5258 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.
摘要翻译：公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。使用镶嵌工艺完成制作。金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。金属结构可用作耐腐蚀保险丝。金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。电阻器结构可以形成在电介质槽的壁上。该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。电阻可以与MOSFET或其他结构串联。

85. 发明授权

US06570256B2 Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates 有权
标题翻译：碳分级层，用于改善低k电介质与硅衬底的粘附性
公开(公告)号：US06570256B2
公开(公告)日：2003-05-27
申请号：US09910380
申请日：2001-07-20
申请人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
发明人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
IPC分类号： H01L2348
CPC分类号： H01L21/28185 , H01L21/02126 , H01L21/02274 , H01L21/28194 , H01L21/31633 , H01L23/5329 , H01L23/53295 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
摘要翻译：公开了一种在衬底上方具有碳分级层的绝缘体层的结构和方法，其中在衬底上方的每个连续的碳分级层中碳的浓度增加。绝缘体包括介电常数小于3.3的低k电介质。碳分级层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘合性。该结构还可以包括碳分级层之间的稳定界面。更具体地，碳分级层包括邻近基底的第一层，其碳含量在约5％至20％之间，第一层上方的碳含量在约10％至30％之间，第三层在第二层上方具有约20％至40％的碳含量。

86. 发明授权

US06465376B2 Method and structure for improving electromigration of chip interconnects 失效
标题翻译：改善芯片互连电迁移的方法和结构
公开(公告)号：US06465376B2
公开(公告)日：2002-10-15
申请号：US09377337
申请日：1999-08-18
申请人： Cyprian Emeka Uzoh , Daniel C. Edelstein , Andrew Simon
发明人： Cyprian Emeka Uzoh , Daniel C. Edelstein , Andrew Simon
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76883 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10S977/891 , H01L2924/00
摘要： A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.
摘要翻译：微结构包括在基底上的铝，铜或其合金的导电层，其中该层包含至少约0.1微米的金属颗粒，以及沉积在金属表面的晶界中的阻挡材料及其制造方法。

87. 发明授权

US06297140B1 Method to plate C4 to copper stud 有权
标题翻译： C4到铜柱的方法
公开(公告)号：US06297140B1
公开(公告)日：2001-10-02
申请号：US09389232
申请日：1999-09-03
申请人： Cyprian Emeka Uzoh , Daniel C. Edelstein
发明人： Cyprian Emeka Uzoh , Daniel C. Edelstein
IPC分类号： H01L2144
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03602 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/1148 , H01L2224/13006 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/3025 , Y10T428/12299 , Y10T428/12361 , H01L2924/00014 , H01L2224/05552
摘要： A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.
摘要翻译：一种在不使用掩模的情况下将第二金属直接镀在第一金属上的方法。提供了包括至少一个金属特征和覆盖金属特征和基底的至少一个绝缘层的半导体基板。在至少一个绝缘层中形成至少一个凹槽，从而暴露出金属特征的至少一部分。在绝缘层和金属特征的暴露部分之上形成至少一个导电阻挡层。在至少一个阻挡层上形成第一金属的电镀种子层。在电镀种子层上沉积光致抗蚀剂层。除去光致抗蚀剂层的一部分和至少一个凹部外部的电镀种子层的部分。残留在至少一个凹部中的光致抗蚀剂被去除。第二金属被电镀到凹槽中的电镀种子层，使用阻挡层传导电流。

88. 发明授权

US08669182B2 Metal cap with ultra-low κ dielectric material for circuit interconnect applications 有权
标题翻译：金属盖带有超低kappa电介质材料用于电路互连应用
公开(公告)号：US08669182B2
公开(公告)日：2014-03-11
申请号：US13398070
申请日：2012-02-16
申请人： Chih-Chao Yang , Daniel C. Edelstein
发明人： Chih-Chao Yang , Daniel C. Edelstein
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76885 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.
摘要翻译：提供了一种互连结构，其具有增强的电迁移可靠性，而不降低电路短产量，并且提高了技术可扩展性。本发明的互连结构包括具有约3.0或更小的介电常数的电介质材料。电介质材料具有嵌入其中的至少一种导电材料。贵金属盖直接位于至少一个导电区域的上表面上。贵金属帽基本上不延伸到与至少一个导电区域相邻的电介质材料的上表面上，并且贵金属帽材料不会沉积在电介质表面上。还提供了利用低温（约300℃或更低）化学沉积工艺制造这种互连结构的方法。

89. 发明申请

US20140061914A1 DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING 有权
公开(公告)号：US20140061914A1
公开(公告)日：2014-03-06
申请号：US13599256
申请日：2012-08-30
申请人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
发明人： Thomas W. Dyer , Daniel C. Edelstein , Tze-man Ko , Andrew H. Simon , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76886 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

90. 发明申请

US20140021616A1 SEMICONDUCTOR STRUCTURE 审中-公开
标题翻译：半导体结构
公开(公告)号：US20140021616A1
公开(公告)日：2014-01-23
申请号：US13553559
申请日：2012-07-19
申请人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
发明人： Diego Anzola , Evan G. Colgan , Kevin K. Dezfulian , Daniel C. Edelstein , Mark C. H. Lamorey , Sampath Purushothaman , Thomas M. Shaw , Roy R. Yu
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/585 , H01L23/562 , H01L25/0657 , H01L2224/04042 , H01L2224/05624 , H01L2225/06551 , H01L2225/06565
摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.
摘要翻译：提供半导体结构，并且包括具有边缘表面的基底和具有中心区域的器件表面，设置在器件表面上的裂纹阻挡结构以及包括设置在中心区域的器件表面上的部件的电路结构，并将电耦合到组件。互连构造成在桥接在裂纹停止结构上的同时从中心区域延伸到边缘表面。

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