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1. 发明授权

US06992390B2 Liner with improved electromigration redundancy for damascene interconnects 失效
标题翻译：具有改进的大马士革互连的电迁移冗余的衬垫
公开(公告)号：US06992390B2
公开(公告)日：2006-01-31
申请号：US10702651
申请日：2003-11-07
申请人： Daniel C. Edelstein , Baozhen Li , Timothy D. Sullivan
发明人： Daniel C. Edelstein , Baozhen Li , Timothy D. Sullivan
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure for semiconductor integrated circuits is disclosed. The interconnection structure comprises a redundant layer, and at least one adhesion/diffusion barrier layer. The redundant layer comprises a metal or metal alloy selected from Ta, Mo, W, Be, Cr, Co, Ir, Ni, Nb, Os, Pd, Pt, Rb, Rh, Ru, and Th.
摘要翻译：公开了一种用于半导体集成电路的互连结构。互连结构包括冗余层和至少一个粘附/扩散阻挡层。冗余层包括选自Ta，Mo，W，Be，Cr，Co，Ir，Ni，Nb，Os，Pd，Pt，Rb，Rh，Ru和Th中的金属或金属合金。

2. 发明申请

US20130328167A1 SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR 审中-公开
标题翻译：自对准金属绝缘子 - 金属（MIM）电容器
公开(公告)号：US20130328167A1
公开(公告)日：2013-12-12
申请号：US13489940
申请日：2012-06-06
申请人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/75 , H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.
摘要翻译：提供集成在后端（BEOL）结构中的金属 - 绝缘体 - 金属（MIM）电容器结构。 MIM电容器结构包括嵌入在BEOL结构的电介质材料中的下电极，即第一导电材料，具有等于或大于位于下电极顶部的二氧化硅的介电常数的介电材料衬垫，以及位于电介质材料衬垫的垂直部分之间并且位于介电材料衬里的水平连接部分顶部的上电极，即第二导电材料。根据本公开，电介质材料衬垫的垂直部分不延伸到包括下电极的电介质材料的上表面上。

3. 发明申请

US20120261793A1 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 有权
标题翻译：电保险丝及其制造方法
公开(公告)号：US20120261793A1
公开(公告)日：2012-10-18
申请号：US13085568
申请日：2011-04-13
申请人： Chih-Chao Yang , Stephen M. Gates , Baozhen Li , Daniel C. Edelstein
发明人： Chih-Chao Yang , Stephen M. Gates , Baozhen Li , Daniel C. Edelstein
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.
摘要翻译：一种改进的电熔丝（e-fuse）装置，包括具有第一顶表面的电介质层，嵌入介质层中的两个导电特征和熔丝元件。每个导电特征具有第二顶表面和直接在第二顶表面上的金属帽。每个金属盖具有在介电层的第一顶表面之上的第三顶表面。熔丝元件位于每个金属盖的第三顶表面上，并位于介质层的第一顶表面上。还提供了形成电熔丝装置的方法。

4. 发明申请

US20120119366A1 ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT 有权
标题翻译：通过电路互连连接
公开(公告)号：US20120119366A1
公开(公告)日：2012-05-17
申请号：US13356013
申请日：2012-01-23
申请人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
发明人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
IPC分类号： H01L23/532
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译：在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触重叠变化。

5. 发明授权

US08114768B2 Electromigration resistant via-to-line interconnect 有权
标题翻译：防电互连线路互连
公开(公告)号：US08114768B2
公开(公告)日：2012-02-14
申请号：US12344838
申请日：2008-12-29
申请人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
发明人： Baozhen Li , Paul S. McLaughlin , Timothy D. Sullivan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译：在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触重叠变化。

6. 发明授权

US07500208B2 Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime 有权
标题翻译：在深亚微米体系的半导体集成电路中的导电线的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US07500208B2
公开(公告)日：2009-03-03
申请号：US11673369
申请日：2007-02-09
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有部分的电阻来确定第一行几何调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

7. 发明授权

US07692439B2 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

8. 发明授权

US07231617B2 Determination of grain sizes of electrically conductive lines in semiconductor integrated circuits 有权
标题翻译：确定半导体集成电路中导电线的晶粒尺寸
公开(公告)号：US07231617B2
公开(公告)日：2007-06-12
申请号：US10711418
申请日：2004-09-17
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。可以在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

9. 发明授权

US07173338B2 Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing 有权
标题翻译：局部金属沉淀形成的抑制和半导体加工中相应的金属化消耗
公开(公告)号：US07173338B2
公开(公告)日：2007-02-06
申请号：US10708486
申请日：2004-03-06
申请人： Jonathan D. Chapple-Sokol , Terence B. Hook , Baozhen Li , Thomas L. McDevitt , Christopher A. Ponsolle , Bette B. Reuter , Timothy D. Sullivan , Jeffrey S. Zimmerman
发明人： Jonathan D. Chapple-Sokol , Terence B. Hook , Baozhen Li , Thomas L. McDevitt , Christopher A. Ponsolle , Bette B. Reuter , Timothy D. Sullivan , Jeffrey S. Zimmerman
IPC分类号： H01L23/48
CPC分类号： H01L21/7684 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.
摘要翻译：用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。可以在金属线周围形成监测斜坡端子并与金属线电断开。通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

10. 发明授权

US07639032B2 Structure for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力导致退化的结构
公开(公告)号：US07639032B2
公开(公告)日：2009-12-29
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

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