专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20070064464A1 High performance flash memory device capable of high density data storage 有权
标题翻译：高性能闪存设备能够进行高密度数据存储
公开(公告)号：US20070064464A1
公开(公告)日：2007-03-22
申请号：US11229527
申请日：2005-09-20
申请人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Le
发明人： Tiao-Hua Kuo , Nancy Leong , Nian Yang , Guowei Wang , Aaron Lee , Sachit Chandra , Michael VanBuskirk , Johnny Chen , Darlene Hamilton , Binh Le
IPC分类号： G11C17/00
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.
摘要翻译：提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。预定数量的位同时被编程到阵列中的对应存储器单元。同时验证阵列中预定位数的编程状态。

82. 发明授权

US06734028B1 Method of detecting shallow trench isolation corner thinning by electrical stress 失效
标题翻译：通过电应力检测浅沟槽隔离角变薄的方法
公开(公告)号：US06734028B1
公开(公告)日：2004-05-11
申请号：US10113152
申请日：2002-03-28
申请人： Tien-Chun Yang , Nian Yang , Hyeon-Seag Kim
发明人： Tien-Chun Yang , Nian Yang , Hyeon-Seag Kim
IPC分类号： H01L2166
CPC分类号： H01L22/34 , G01R31/275 , G01R31/2831
摘要： A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness may be observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.
摘要翻译：一种用于测试包括浅沟槽隔离（STI）边缘结构的半导体的方法和装置。边缘密集的浅沟槽隔离结构（500）耦合到电压源（310），并记录电流对电压曲线。在同一晶片上的平面结构（600）被耦合到电压源并且记录电流对电压曲线。对两个结构都施加电应力。在电应力之后，获得每个结构的附加电流分布。对于两种类型的结构获得的差异电流曲线的比较可以指示STI拐角效应的存在和/或程度。更具体地，大于平面结构（600）的归一化栅极电流差的STI边缘强化结构（500）的归一化栅极电流差的值表示STI拐角中的电子捕获速率增加，这可以指示 STI角落太薄了。以这种新颖的方式，可以在非破坏性电气测试过程中观察到STI拐角厚度，从而导致使用STI工艺的半导体的更高质量和更高的可靠性。

83. 发明授权

US07746706B2 Methods and systems for memory devices 有权
标题翻译：存储器件的方法和系统
公开(公告)号：US07746706B2
公开(公告)日：2010-06-29
申请号：US11639935
申请日：2006-12-15
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0475
摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及访问存储器单元的方法。在该方法中，擦除存储单元的至少一位。在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。还公开了其它方法和系统。

84. 发明授权

US07613044B2 Method and apparatus for high voltage operation for a high performance semiconductor memory device 有权
标题翻译：用于高性能半导体存储器件的高电压操作的方法和装置
公开(公告)号：US07613044B2
公开(公告)日：2009-11-03
申请号：US11950811
申请日：2007-12-05
申请人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
发明人： Nian Yang , Boon-Aik Ang , Yonggang Wu , Guowei Wang , Fan Wan Lai
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C7/10
CPC分类号： G11C7/1039 , G11C8/08 , G11C16/0475 , G11C16/0491 , G11C16/08 , G11C16/30 , G11C2207/2245
摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).
摘要翻译：提供了一种用于在半导体存储器件（100）的选定存储单元（200）上进行高性能，高电压存储器操作的方法和装置。在编程或擦除操作期间，高电压发生器（106）在所选择的字线（502）上提供连续的高电压电平（702），并且向位线解码器（120）保持连续的高电压电平供应，位线解码器（120）依次提供高电压电平（706）到位线（504）的第一部分，并且在将高电压电平提供给第二部分（710）之前对那些位线（504）进行放电（708）。为了对编程操作进一步改进，高电压发生器（106）通过在其间提供电流控制装置（1208）来解耦提供给字线（502）和位线（504）的高电压，并在时间（1104）以克服由与所选位线（504）和/或位线解码器（120）相关联的电容器负载导致的电压电平下降（1102），所述位线（504）的第二部分预充电（1716）同时向第一部分提供高电压电平以对存储单元（200）的第一部分进行编程（1706）。为了改进读取操作，动态参考单元（2002）是空白的是通过从第一电压源（2112）到动态参考单元（2002）和从第二电压源（2104）提供非相同调节的高电压电平来确定的）到静态参考单元（2004），并且如果动态参考单元（2002）不为空白，则通过向所选择的存储单元（200），动态参考单元（200）提供相同调节的高电压电平来读取所选存储单元（200） 2002）和静态参考单元（2004）。

85. 发明授权

US07532518B2 Compensation method to achieve uniform programming speed of flash memory devices 有权
标题翻译：补偿方法实现闪存器件的均匀编程速度
公开(公告)号：US07532518B2
公开(公告)日：2009-05-12
申请号：US11767622
申请日：2007-06-25
申请人： Nian Yang , Fan Wan Lai , Aaron Lee
发明人： Nian Yang , Fan Wan Lai , Aaron Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/10
摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.
摘要翻译：本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

86. 发明申请

US20090119447A1 CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY 有权
标题翻译：非线性存储器中的通道擦除的控制位线放电
公开(公告)号：US20090119447A1
公开(公告)日：2009-05-07
申请号：US11935717
申请日：2007-11-06
申请人： Aaron Lee , Nian Yang , Jiani Zhang
发明人： Aaron Lee , Nian Yang , Jiani Zhang
IPC分类号： G06F12/00
CPC分类号： G11C16/0416 , G11C11/5635 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.
摘要翻译：提出了有助于以受控的速率放电与非易失性存储器中的存储器阵列相关联的位线（BL）的系统和/或方法。放电元件有助于以期望的速率放电BL，从而防止在与非易失性存储器相关联的y解码器组件内发生“热切换”现象。放电部件可以部分地由控制BL放电速率的放电晶体管部件组成，其中放电晶体管部件的栅极电压可以由放电控制器部件控制。 BL放电的速率可以由设计中使用的放电晶体管组件的大小，y解码器组件的强度和/或尺寸，特定存储器件发生的擦除错误的数量和/或其他因素，以便于防止发生热切换。

87. 发明申请

US20080316830A1 COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES 有权
标题翻译：用于实现闪存存储器件的均匀编程速度的补偿方法
公开(公告)号：US20080316830A1
公开(公告)日：2008-12-25
申请号：US11767622
申请日：2007-06-25
申请人： Nian Yang , Fan Wan Lai , Aaron Lee
发明人： Nian Yang , Fan Wan Lai , Aaron Lee
IPC分类号： G11C7/00
CPC分类号： G11C16/30 , G11C16/10
摘要： Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array.
摘要翻译：本文提供的系统和方法用于提高闪存设备中的操作速度均匀性。由于典型的闪存阵列的特征，存储器阵列中的存储器单元可能经历分布式衬底电阻，随着存储器单元与存储器阵列的边缘的距离增加而增加。分布式基板电阻的这种差异可以根据其位置改变提供给存储器阵列中的不同存储单元的电压，这进而导致存储器阵列上的高电压操作的速度（例如编程）的不一致。本文提供的系统和方法通过至少部分地基于每个相应存储器单元的位置，通过向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性。例如，可以提供补偿操作电压，其在存储器阵列的中心附近较高，并且在存储器阵列的边缘附近较低，从而减小分布式衬底电阻的影响并且提供整个存储器阵列中的增加的操作速度均匀性。

88. 发明申请

US20080151639A1 FLASH MEMORY DEVICE WITH EXTERNAL HIGH VOLTAGE SUPPLY 有权
标题翻译：具有外部高压电源的闪存存储器件
公开(公告)号：US20080151639A1
公开(公告)日：2008-06-26
申请号：US11613383
申请日：2006-12-20
申请人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
发明人： Nian Yang , Yonggang Wu , Aaron Lee , Wei Daisy Cai
IPC分类号： G11C16/32
CPC分类号： G11C16/12
摘要： A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period. The timing device (318) signals the switch (314) to decouple the high voltage signal (412) and the operational voltage signal (402) from the memory cells (305) in response to the timer activation signal (404) and to recouple the high voltage signal (412) and the operational voltage signal (402) to the memory cells (305) a time delay interval thereafter. The time delay interval is determined in response to the high voltage signal (412).
摘要翻译：提供可选择地连接到外部高压电源（122）的半导体存储器件（104）。半导体存储器件（104）包括开关（314），检测器（316）和定时装置（318）。开关（314）连接到外部电压源信号，并且可选择地将外部电压供应信号耦合到半导体存储器件（104）的存储单元（305），用于存储器操作。包括从外部高压电源（122）提供的高电压信号（412）的外部电压供给信号和操作电压信号Vcc（402）。检测器（316）连接到外部电压源信号，以响应于检测到工作电压通电周期而产生定时器激活信号（404）。定时装置（318）响应于定时器启动信号（404），向开关314通知高压信号412和操作电压信号402与存储单元305的耦合，高电压信号（412）和操作电压信号（402）到其后的时间延迟区间。响应于高电压信号确定时间延迟间隔（412）。

89. 发明申请

US20080144391A1 Methods and systems for memory devices 有权
标题翻译：存储器件的方法和系统
公开(公告)号：US20080144391A1
公开(公告)日：2008-06-19
申请号：US11639935
申请日：2006-12-15
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C16/10
CPC分类号： G11C16/3404 , G11C16/0475
摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及访问存储器单元的方法。在该方法中，擦除存储单元的至少一位。在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。还公开了其它方法和系统。

90. 发明授权

US07352626B1 Voltage regulator with less overshoot and faster settling time 有权
标题翻译：电压调节器具有较少的过冲和更快的建立时间
公开(公告)号：US07352626B1
公开(公告)日：2008-04-01
申请号：US11212614
申请日：2005-08-29
申请人： Yonggang Wu , Guowei Wang , Nian Yang , Aaron Lee
发明人： Yonggang Wu , Guowei Wang , Nian Yang , Aaron Lee
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C5/14
摘要： A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.
摘要翻译：电压调节器可以包括运算放大器部分，连接到运算放大器部分的输出的电容器和被配置为将电容器连接到电压源的开关。开关被配置为在激活运算放大器部分之前对电容器充电。电容器被配置为存储电荷以补充从运算放大器部分提供的电流。电压调节器可以用于向非易失性存储单元供电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式