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81. 发明申请

US20120060279A1 PULL DOWN BED WITH AUTOMATIC LOCKING DEVICE 有权
标题翻译：带自动锁定装置的下拉床
公开(公告)号：US20120060279A1
公开(公告)日：2012-03-15
申请号：US13264677
申请日：2010-04-21
申请人： Luigi Colombo
发明人： Luigi Colombo
IPC分类号： A47C17/52
CPC分类号： A47C17/52 , A47C17/38
摘要： A pull down bed with automatic locking device has a movable framework, which constitutes a mattress frame, and is hinged to a container body, which constitutes a piece of furniture, so as to define a closed position, in which said mattress frame is substantially inside the piece of furniture, and an open position, for use as a bed, in which the mattress frame is in a horizontal position and rests on the ground by means of two feet. The mattress frame is hinged to the piece of furniture at one end and has its feet at the other end. The pull down bed includes a device for locking said mattress frame in the closed or horizontal position, which is actuated by an actuation device, which includes the feet.
摘要翻译：具有自动锁定装置的下拉床具有可移动的框架，其构成床垫框架，并铰接到构成一件家具的容器主体上，以限定关闭位置，其中所述床垫框架基本上在其内家具和开放位置，用作床，其中床垫框架处于水平位置，并通过两个脚搁置在地面上。床垫框架在一端铰接到一件家具，另一端有脚。下拉床包括用于将所述床垫框架锁定在封闭或水平位置的装置，其由包括脚的致动装置致动。

82. 发明申请

US20110091647A1 GRAPHENE SYNTHESIS BY CHEMICAL VAPOR DEPOSITION 有权
标题翻译：石墨合成化学蒸气沉积
公开(公告)号：US20110091647A1
公开(公告)日：2011-04-21
申请号：US12774342
申请日：2010-05-05
申请人： Luigi Colombo , Xuesong Li , Rodney S. Ruoff
发明人： Luigi Colombo , Xuesong Li , Rodney S. Ruoff
IPC分类号： C23C16/44 , C23C16/26
CPC分类号： C23C16/26 , B82Y30/00 , B82Y40/00 , C01B32/186
摘要： Processes for synthesizing graphene films. Graphene films may be synthesized by heating a metal or a dielectric on a substrate to a temperature between 400° C. and 1,400° C. The metal or dielectric is exposed to an organic compound thereby growing graphene from the organic compound on the metal or dielectric. The metal or dielectric is later cooled to room temperature. As a result of the above process, standalone graphene films may be synthesized with properties equivalent to exfoliated graphene from natural graphite that is scalable to size far greater than that available on silicon carbide, single crystal silicon substrates or from natural graphite.
摘要翻译：合成石墨烯薄膜的方法。石墨烯膜可以通过将基板上的金属或电介质加热到400℃和1400℃之间的温度来合成。将金属或电介质暴露于有机化合物，从而从金属或电介质上的有机化合物生长石墨烯。然后将金属或电介质冷却至室温。作为上述方法的结果，独立的石墨烯膜可以合成具有相当于天然石墨剥离的石墨烯的性质，该石墨烯的尺寸远大于在碳化硅，单晶硅衬底或天然石墨上可获得的尺寸。

83. 发明申请

US20100224851A1 SYNTHESIZING GRAPHENE FROM METAL-CARBON SOLUTIONS USING ION IMPLANTATION 有权
标题翻译：使用离子植入法合成来自金属碳解决方案的石墨
公开(公告)号：US20100224851A1
公开(公告)日：2010-09-09
申请号：US12706116
申请日：2010-02-16
申请人： Luigi Colombo , Robert M. Wallace , Rodney S. Ruoff
发明人： Luigi Colombo , Robert M. Wallace , Rodney S. Ruoff
IPC分类号： H01L29/15 , C04B35/536 , H01L21/20
CPC分类号： H01L21/02612 , H01L21/02527
摘要： A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
摘要翻译：一种使用碳的离子注入合成石墨烯的方法和半导体器件。使用离子注入将碳注入金属中。在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。然后去除金属层。或者，将凹陷区域图案化并蚀刻在位于基底上的电介质层中。金属后来形成在这些凹陷区域。然后使用离子注入将碳注入到金属中。然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。

84. 发明申请

US20090298749A1 DALBAVANCIN COMPOSITIONS FOR TREATMENT OF BACTERIAL INFECTIONS 有权
标题翻译：用于治疗细菌感染的DALBAVANCIN组合物
公开(公告)号：US20090298749A1
公开(公告)日：2009-12-03
申请号：US12476785
申请日：2009-06-02
申请人： Martin Stogniew , Luigi Colombo , Romeo Clabatti
发明人： Martin Stogniew , Luigi Colombo , Romeo Clabatti
IPC分类号： A61K38/14 , A61P31/04
CPC分类号： C07H7/033 , A61K31/704 , A61K38/00 , C07H13/06 , C07H15/203 , C07K9/008 , Y02A50/475 , Y02A50/478 , Y02A50/479 , Y02A50/481 , A61K2300/00
摘要： The invention provides methods and compositions for treatment of bacterial infections. The composition may be a combination of factors, which include A0, A1, B1, B2, C0, C1, isoB0, and MAG, in the presence of low level solvent. Methods of the invention include administration of dalbavancin formulations for treatment of a bacterial infection, in particular a Gram-positive bacterial infection of skin and soft tissue. Dosing regimens include multiple dose administration of dalbavancin, which often remains at therapeutic levels in the bloodstream for at least one week, providing prolonged therapeutic action against a bacterial infection. Dosing regimens for renal patients are also included.
摘要翻译：本发明提供了用于治疗细菌感染的方法和组合物。该组合物可以是低浓度溶剂存在下的A0，A1，B1，B2，C0，C1，isoBO和MAG等因素的组合。本发明的方法包括施用达巴万星制剂用于治疗细菌感染，特别是皮肤和软组织的革兰氏阳性细菌感染。给药方案包括达巴万星的多剂量给药，其通常在血流中保持治疗水平至少一周，为细菌感染提供长时间的治疗作用。还包括肾脏患者的给药方案。

85. 发明授权

US07601577B2 Work function control of metals 有权
标题翻译：金属工作功能控制
公开(公告)号：US07601577B2
公开(公告)日：2009-10-13
申请号：US11870631
申请日：2007-10-11
申请人： James Joseph Chambers , Mark Robert Visokay , Luigi Colombo , Antonio Luis Pacheco Rotondaro
发明人： James Joseph Chambers , Mark Robert Visokay , Luigi Colombo , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译：公开了具有不同功函数的金属栅极晶体管。在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

86. 发明申请

US20090104745A1 INTEGRATION METHOD FOR DUAL DOPED POLYSILICON GATE PROFILE AND CD CONTROL 审中-公开
标题翻译：双重多晶硅门型材和CD控制的集成方法
公开(公告)号：US20090104745A1
公开(公告)日：2009-04-23
申请号：US11877124
申请日：2007-10-23
申请人： Hyesook Hong , Luigi Colombo , Jinhan Choi
发明人： Hyesook Hong , Luigi Colombo , Jinhan Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/823842
摘要： In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of polysilicon gates having a first critical dimension disposed over a dielectric layer and planarizing the plurality of polysilicon gates with a spin-on material to form a plurality of planarized polysilicon gates. The method can further include doping an exposed first region with p-type dopants to form a plurality of p-doped planarized polysilicon gates and doping an exposed second region with n-type dopants to form a plurality of n-doped planarized polysilicon gates. The method can also include removing the spin-on material to form a plurality of p-doped polysilicon gates and a plurality of n-doped polysilicon gates, wherein critical dimension of each of the plurality of n-doped polysilicon gates and the plurality of p-doped polysilicon gates are substantially similar to the first critical dimension.
摘要翻译：根据本教导，提供制造双掺杂多晶硅栅极的方法。该方法可以包括提供包括多个多晶硅栅极的半导体结构，该多晶硅栅极具有设置在电介质层上的第一临界尺寸，并且用旋涂材料平坦化多个多晶硅栅极以形成多个平坦化的多晶硅栅极。该方法还可以包括用p型掺杂剂掺杂暴露的第一区域以形成多个p掺杂的平坦化多晶硅栅极，并用n型掺杂剂掺杂暴露的第二区域以形成多个n掺杂的平坦化多晶硅栅极。该方法还可以包括去除旋涂材料以形成多个p掺杂多晶硅栅极和多个n掺杂多晶硅栅极，其中多个n掺杂多晶硅栅极和多个p掺杂多晶硅栅极中的每一个的临界尺寸掺杂的多晶硅栅极基本上类似于第一临界尺寸。

87. 发明授权

US07351632B2 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon 有权
标题翻译：半导体CMOS器件和方法与NMOS高k电介质之间形成核心PMOS氮氧化硅介质形成之前，采用直接氮化硅
公开(公告)号：US07351632B2
公开(公告)日：2008-04-01
申请号：US11118842
申请日：2005-04-29
申请人： Mark Robert Visokay , Luigi Colombo , James Joseph Chambers
发明人： Mark Robert Visokay , Luigi Colombo , James Joseph Chambers
IPC分类号： H01L21/8238
CPC分类号： H01L27/105 , H01L21/823842 , H01L21/823857 , H01L27/11 , H01L27/1116
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.
摘要翻译：本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。在半导体器件（506）的芯和I / O区域中形成氧化物层。氧化物层从器件的核心区域移除（508）。在芯和I / O区域上形成高k电介质层（510）。然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。通过低温热处理在核心和I / O区域的PMOS区域内生长氮化硅层（516）。随后，进行氧化处理（518），其将氮化硅氧化成氮氧化硅。

88. 发明申请

US20070042555A1 Formation of uniform silicate gate dielectrics 有权
标题翻译：均匀硅酸盐栅极电介质的形成
公开(公告)号：US20070042555A1
公开(公告)日：2007-02-22
申请号：US11205477
申请日：2005-08-17
申请人： Hiroaki Niimi , Luigi Colombo , James Chambers
发明人： Hiroaki Niimi , Luigi Colombo , James Chambers
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8234
CPC分类号： H01L21/823462 , H01L21/28185 , H01L21/28229 , H01L21/31645 , H01L21/823857 , H01L21/8249 , H01L29/517
摘要： The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).
摘要翻译：本发明提供了形成栅极电介质的方法，其包括在衬底（110）上形成包括金属和至少一种非金属元素的金属源层（210）。金属源层（210）形成为具有富含金属的组成。在金属源层（210）之上形成包括金属的电介质层（310）。

89. 发明申请

US20070037335A1 Dual work function CMOS devices utilizing carbide based electrodes 有权
标题翻译：利用碳化物电极的双功能CMOS器件
公开(公告)号：US20070037335A1
公开(公告)日：2007-02-15
申请号：US11204235
申请日：2005-08-15
申请人： James Chambers , Luigi Colombo , Mark Visokay
发明人： James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译：同时形成具有各自功函数的不同金属栅极晶体管。在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。

90. 发明申请

US20060267119A1 REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件中工作功能的基于金属的金属电极
公开(公告)号：US20060267119A1
公开(公告)日：2006-11-30
申请号：US11462573
申请日：2006-08-04
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译：本发明在一个实施例中提供一种栅极结构（100）。栅极结构包括栅极电介质（105）和栅极（110）。栅极电介质包括难熔金属并且位于半导体衬底（115）之上。半导体衬底具有导带和价带。栅极位于栅极电介质上方并且包括难熔金属。栅极具有与导带或价带对准的功函数。其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

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