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    • 87. 发明授权
    • Memory cell having stressed layers
    • 具有应力层的记忆单元
    • US07678662B2
    • 2010-03-16
    • US11609851
    • 2006-12-12
    • Reza ArghavaniEllie YiehHichem M'Saad
    • Reza ArghavaniEllie YiehHichem M'Saad
    • H01L21/76
    • H01L29/7846H01L27/105H01L27/1052H01L29/66825H01L29/7883
    • A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.
    • 存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底,其在沟道周围形成源极和漏极。 通道上的层叠层包括(i)隧道氧化物层,(ii)浮动栅极,(iii)栅极间电介质和(iv)控制栅极。 源极和漏极上的多晶硅层。 覆盖层叠层的覆盖层包括间隔层和预金属沉积层。 可选地,使用触点来接触源极,漏极和硅化物层中的每一个,并且每个都具有暴露部分。 围绕n掺杂区域提供浅的隔离沟槽,沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。 应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。