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81. 发明授权

US07958408B2 On-chip receiver sensitivity test mechanism 有权
标题翻译：片上接收机灵敏度测试机制
公开(公告)号：US07958408B2
公开(公告)日：2011-06-07
申请号：US11835274
申请日：2007-08-07
申请人： Elida Isabel de Obaldia , Dirk Leipold , Oren Eliezer , Ran Katz , Bogdan Staszewski
发明人： Elida Isabel de Obaldia , Dirk Leipold , Oren Eliezer , Ran Katz , Bogdan Staszewski
IPC分类号： H04B17/00
CPC分类号： H04B17/0085 , G01R31/2822 , H04B17/29 , H04L1/24
摘要： An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.
摘要翻译：用于集成RF发射机的片上接收机灵敏度测试机构，其中发射机和接收机共享相同的振荡器。该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要，并且允许使用非常低成本的外部RF测试设备。本发明利用已经存在于收发器中的电路，即调制电路和本地振荡器来执行灵敏度测试。片上LO用于产生调制测试信号，否则将需要由具有调制能力的昂贵的外部RF测试设备提供。调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号，随后由接收器链的其余部分处理。恢复的数据位使用片上BER计或计数器进行比较，产生BER读数。 BER读取在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

82. 发明授权

US07575969B2 Buried layer and method 有权
标题翻译：埋层和方法
公开(公告)号：US07575969B2
公开(公告)日：2009-08-18
申请号：US09798106
申请日：2001-03-02
申请人： Dirk Leipold
发明人： Dirk Leipold
IPC分类号： H01L21/8238
CPC分类号： H01L28/10 , H01L27/0629
摘要： A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations.
摘要翻译：用于RF无源操作的高电阻率硅，其包括具有植入的CMOS阱的CMOS结构以及在井注入期间由深埋入物形成的阱下的掩埋层。

83. 发明申请

US20070008199A1 Negative contributive offset compensation in a transmit buffer utilizing inverse clocking 有权
标题翻译：使用反向时钟的发送缓冲器中的负贡献偏移补偿
公开(公告)号：US20070008199A1
公开(公告)日：2007-01-11
申请号：US11178993
申请日：2005-07-11
申请人： Sameh Rezeq , Dirk Leipold , Robert Staszewski , Chih-Ming Hung
发明人： Sameh Rezeq , Dirk Leipold , Robert Staszewski , Chih-Ming Hung
IPC分类号： H03M1/06
CPC分类号： H03F1/0205 , H03F1/3241 , H03F2200/331 , H03F2200/375 , H03M3/356 , H03M3/50 , H03M7/3026 , H03M7/3037 , H04L27/368
摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.
摘要翻译：一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。来自Σ-Δ调制器的正输出的处理方式与负输出不同。与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。时钟的非反相版本与正输出一起使用，反时限与负输出一起使用。使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。结果是具有零偏移的偏移补偿RF输出信号。

84. 发明授权

US07035750B2 On-chip test mechanism for transceiver power amplifier and oscillator frequency 有权
标题翻译：收发器功率放大器和振荡器频率的片上测试机制
公开(公告)号：US07035750B2
公开(公告)日：2006-04-25
申请号：US10759912
申请日：2004-01-16
申请人： Elida Isabel de Obaldia , Chih-Ming Hung , Dirk Leipold , Oren Eliezer
发明人： Elida Isabel de Obaldia , Chih-Ming Hung , Dirk Leipold , Oren Eliezer
IPC分类号： G01R31/00
CPC分类号： H03K5/08 , H04B17/102 , H04B17/16 , H04B17/20
摘要： An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.
摘要翻译：用于收发器功率放大器和振荡器频率的片上测试机制，用于集成RF收发器的发射器部分。发射机功率放大器的RF输出被输入到具有可配置阈值的内置专用模拟比较器。阈值被调整到在比较器输出处开始发生交叉的预定电平。仅当功率放大器输出高于最小可配置电平时，比较器才会输出脉冲。比较器输出被输入到分频器，其频率输出由低成本外部测试仪测试以确定实际RF频率，从而确认产生正确的振荡器频率，并且功率放大器输出端的信号幅度足够可以超过可配置的阈值电平，从而确定输出功率与其规定的规格的一致性。

85. 发明授权

US07023272B2 Multi-band low noise amplifier system 有权
标题翻译：多频段低噪声放大器系统
公开(公告)号：US07023272B2
公开(公告)日：2006-04-04
申请号：US10827577
申请日：2004-04-19
申请人： Chih-Ming Hung , Dirk Leipold , Yo-Chuol Ho
发明人： Chih-Ming Hung , Dirk Leipold , Yo-Chuol Ho
IPC分类号： H03F3/68
CPC分类号： H03F3/45179 , H03F1/223 , H03F1/565 , H03F3/193 , H03F2200/294 , H03F2200/372 , H03F2200/492 , H03F2203/45394 , H03F2203/7209
摘要： A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output matching that can be tuned by an adjustable inductor together with a tunable capacitor bank.
摘要翻译：低噪声放大器（LNA）在多个频带上工作，而占用比已知LNA实现更少的硅面积。 LNA包括可调谐电感器和可调电容器组一起调谐的输出匹配。

86. 发明申请

US20050195917A1 Method and apparatus for crystal drift compensation 审中-公开
标题翻译：晶体漂移补偿方法和装置
公开(公告)号：US20050195917A1
公开(公告)日：2005-09-08
申请号：US10883501
申请日：2004-06-30
申请人： Robert Staszewski , Dirk Leipold
发明人： Robert Staszewski , Dirk Leipold
IPC分类号： H04L27/04
CPC分类号： H03J7/047 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03L1/00 , H03L2207/50
摘要： A mobile device includes frequency synthesizer circuitry for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator, without frequency stabilization circuitry. Variations in the output of the crystal oscillator are compensated by adjusting the multiplication factor of the frequency synthesizer.
摘要翻译：移动设备包括用于以参考频率的倍数产生频道频率的频率合成器电路。参考频率由自由运行的晶体振荡器产生，没有频率稳定电路。通过调整频率合成器的乘法因子来补偿晶体振荡器输出的变化。

87. 发明授权

US06882829B2 Integrated circuit incorporating RF antenna switch and power amplifier 有权
标题翻译：集成电路结合RF天线开关和功率放大器
公开(公告)号：US06882829B2
公开(公告)日：2005-04-19
申请号：US10114227
申请日：2002-04-02
申请人： Alexander Mostov , Dirk Leipold
发明人： Alexander Mostov , Dirk Leipold
IPC分类号： H04B1/04 , H04B1/48 , H04B1/44
CPC分类号： H04B1/48 , H04B1/04
摘要： A novel integrated circuit incorporating a transmit/receive antenna switch capable of being integrated using silicon based RF CMOS semiconductor processes and a power amplifier on the same substrate. The switch circuit is constructed whereby the substrate (i.e. bulk) terminals of the FETs are left floating thus improving the isolation and reducing the insertion loss of the switch. Floating the substrate of the transistors eliminates most of the losses caused by leakage paths through parasitic capacitances internal to the transistor thus improving the isolation and reducing the insertion loss of the switch. Alternatively, the substrate can be connected to the source or to ground via a resistor of sufficiently high value to effectively float the substrate.
摘要翻译：一种新颖的集成电路，其结合了能够使用硅基RF CMOS半导体工艺集成的发射/接收天线开关和在同一衬底上的功率放大器。开关电路被构造成使得FET的衬底（即本体）端子悬空，从而改善隔离并降低开关的插入损耗。浮置晶体管的基板消除了由通过晶体管内部的寄生电容的泄漏路径引起的大部分损耗，从而改善了隔离并降低了开关的插入损耗。或者，衬底可以通过足够高的电阻器连接到源极或接地，以有效地浮动衬底。

88. 发明申请

US20090207940A1 Predistortion Calibration In A Transceiver Assembly 审中-公开
标题翻译：收发器组件中的预失真校准
公开(公告)号：US20090207940A1
公开(公告)日：2009-08-20
申请号：US12432447
申请日：2009-04-29
申请人： Robert Bogdan Staszewski , Dirk Leipold
发明人： Robert Bogdan Staszewski , Dirk Leipold
IPC分类号： H04L25/03 , H04L25/49
CPC分类号： H03F1/3282 , H03F1/0211 , H03F1/3247 , H03F2200/331
摘要： Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.
摘要翻译：提供了用于校准集成收发器电路中的数字预失真器的系统和方法。数字发射器路径提供来自数字输入的信号。发射机路径包括数字预失真器，其预失真数字输入以减轻与功率放大器相关联的非线性。集成收发器电路还包括与数字发送器路径相关联的接收器路径。耦合元件提供从发射机路径到接收机路径的信号。信号评估器基于该信号确定与数字预失真器相关联的至少一个参数的值。

89. 发明申请

US20090096525A1 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US20090096525A1
公开(公告)日：2009-04-16
申请号：US12134464
申请日：2008-06-06
申请人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
发明人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
IPC分类号： H03F3/21 , H03F3/68 , H03F1/02
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement power control in a digital power amplifier are described.
摘要翻译：描述了在数字功率放大器中实现功率控制的方法。

90. 发明申请

US20080157839A1 TIME-TO-DIGITAL CONVERTER WITH NON-INVERTING BUFFERS, TRANSMISSION GATES AND NON-LINEARITY CORRECTOR, SOC INCLUDING SUCH CONVERTER AND METHOD OF PHASE DETECTION FOR USE IN SYNTHESIZING A CLOCK SIGNAL 有权
标题翻译：具有非反相缓冲器，传输门和非线性校正器的时间到数字转换器，包括这种转换器的SOC以及用于合成时钟信号的相位检测方法
公开(公告)号：US20080157839A1
公开(公告)日：2008-07-03
申请号：US11690506
申请日：2007-03-23
申请人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
发明人： Robert Bogdan Staszewski , Dirk Leipold , Wei Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , H03L2207/50
摘要： A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.
摘要翻译：时间数字转换器（TDC），包括TDC的片上系统，用于合成时钟信号的相位检测方法和用于TDC的非线性校正器。在一个实施例中，TDC包括被配置为接收时钟信号并产生延迟的时钟信号的延迟元件链。每个延迟元件包括：（1）非反相缓冲器，被配置为将时钟信号延迟约两倍的逆变器的延迟以提供缓冲器延迟的时钟信号，以及（2）耦合到非反相缓冲器的第一传输门反相缓冲器并且被配置为将时钟信号延迟大约逆变器的延迟以提供第一门延迟的时钟信号。

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