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81. 发明授权

US08355289B2 Memory device, semiconductor memory device and control method thereof 有权
公开(公告)号：US08355289B2
公开(公告)日：2013-01-15
申请号：US12461770
申请日：2009-08-24
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.

82. 发明授权

US07869294B2 Semiconductor device having single-ended sensing amplifier 有权
标题翻译：具有单端感测放大器的半导体器件
公开(公告)号：US07869294B2
公开(公告)日：2011-01-11
申请号：US12382494
申请日：2009-03-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/02
CPC分类号： G11C8/08 , G11C7/067 , G11C11/22 , G11C11/223 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
摘要： A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit.
摘要翻译：具有分层位线结构的半导体存储装置中的单端读出放大器包括：第一MOS晶体管，用于将从存储单元输出的信号放大到位线;第二MOS晶体管，用于将第一MOS晶体管的输出馈送到全局位线和全局位线电压确定电路; 并且包括全局位线电压确定电路的至少第二MOS晶体管的ON / OFF定时或包括全局位线电压确定电路的全局读出放大器的读取定时由包括第一MOS晶体管的复制品的延迟电路的输出信号控制以及全局位线电压确定电路的副本。

83. 发明授权

US08605532B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US08605532B2
公开(公告)日：2013-12-10
申请号：US13299285
申请日：2011-11-17
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.
摘要翻译：本文公开了一种半导体器件，包括存储器单元，耦合到存储器单元的局部位线，对应于局部位线提供的全局位线，以及耦合在局部位线和全局位线之间的位线控制电路。位线控制电路包括在刷新模式下被激活以在与全局位线电隔离的同时刷新存储器单元的数据的恢复电路。

84. 发明申请

US20120127816A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE 有权
标题翻译：具有分层线结构的半导体器件
公开(公告)号：US20120127816A1
公开(公告)日：2012-05-24
申请号：US13299285
申请日：2011-11-17
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/06 , G11C11/402
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.
摘要翻译：本文公开了一种半导体器件，包括存储器单元，耦合到存储器单元的局部位线，对应于局部位线提供的全局位线，以及耦合在局部位线和全局位线之间的位线控制电路。位线控制电路包括在刷新模式下被激活以在与全局位线电隔离的同时刷新存储器单元的数据的恢复电路。

85. 发明授权

US08621135B2 Semiconductor memory device and information data processing apparatus including the same 有权
公开(公告)号：US08621135B2
公开(公告)日：2013-12-31
申请号：US12987784
申请日：2011-01-10
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G06F12/00
CPC分类号： G11C7/1042 , G11C7/1012 , G11C7/1018 , G11C11/4087
摘要： A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship.

86. 发明授权

US08611122B2 Semiconductor memory device having vertical transistors 有权
标题翻译：具有垂直晶体管的半导体存储器件
公开(公告)号：US08611122B2
公开(公告)日：2013-12-17
申请号：US13064942
申请日：2011-04-27
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C5/02 , G11C5/06 , G11C11/40 , G11C11/401 , G11C11/21 , G11C11/24 , G11C11/34
CPC分类号： G11C5/06 , G11C5/025 , G11C11/4097 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10897
摘要： A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding one of the first memory elements and a lower electrode, the first switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the first selective transistors through a first signal line, a second region arranged to make a first line with the first region in a first direction and including a plurality of second memory elements and a plurality of second vertical transistors, the second vertical transistors comprising a plurality of second selective transistors and a second switching transistor, and a third region sandwiched between the first and the second regions.
摘要翻译：一种器件包括包括多个第一存储器元件和多个第一垂直晶体管的第一区域，所述第一垂直晶体管包括多个第一选择晶体管和第一开关晶体管，每个第一选择晶体管包括上电极，第一存储器元件和下电极中的相应一个，第一开关晶体管包括通过第一信号线共同连接到第一选择晶体管的下电极的上电极和下电极，第二区域被布置成使第一线与第一区域在第一方向上并且包括多个第二存储器元件和多个第二垂直晶体管，第二垂直晶体管包括多个第二选择晶体管和第二开关晶体管，以及第三区域，第一和第二个地区。

87. 发明授权

US08593895B2 Semiconductor device and control method thereof 失效
标题翻译：半导体装置及其控制方法
公开(公告)号：US08593895B2
公开(公告)日：2013-11-26
申请号：US13404940
申请日：2012-02-24
申请人： Shinichi Takayama , Kazuhiko Kajigaya
发明人： Shinichi Takayama , Kazuhiko Kajigaya
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4094 , G11C29/06 , G11C29/12005 , G11C2029/1204
摘要： Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches.
摘要翻译：本文公开了一种半导体器件，其包括具有分级位线结构的阵列，彼此相邻的全局位线，对应于全局位线的局部位线，分层开关，预充电全局位线的预充电电路，预充电电路对本地位线和控制电路。当对阵列进行测试时，全局位线的预充电电压被设置为彼此不同的电位，并且控制电路通过全局位线和分层开关控制施加到局部位线的电位。

88. 发明授权

US08472272B2 Semiconductor device having hierarchical bit line structure 失效
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US08472272B2
公开(公告)日：2013-06-25
申请号：US13373006
申请日：2011-11-02
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C11/4097 , G11C7/02 , G11C11/406 , G11C11/4094
摘要： A semiconductor device of the invention comprise a memory cell array configured with hierarchical local bit lines and global bit lines, in which there are provide local bit lines, global bit lines, switches controlling a connection between the global bit lines, sense amplifiers, and a control circuit controlling the switches. In a first period, each sense amplifier amplifies a signal of one of adjacent global bit lines, and in a second period, each sense amplifier amplifies a signal of the other thereof. Accordingly, coupling between the global bit lines can be suppressed.
摘要翻译：本发明的半导体器件包括配置有分层局部位线和全局位线的存储单元阵列，其中提供局部位线，全局位线，控制全局位线，读出放大器和控制电路控制开关。在第一周期中，每个读出放大器放大相邻全局位线之一的信号，并且在第二周期中，每个读出放大器放大另一个的另一个的信号。因此，可以抑制全局位线之间的耦合。

89. 发明申请

US20120063241A1 Semiconductor device and control method thereof 失效
标题翻译：半导体装置及其控制方法
公开(公告)号：US20120063241A1
公开(公告)日：2012-03-15
申请号：US13137745
申请日：2011-09-09
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/10
CPC分类号： G11C11/4097 , G11C2207/005
摘要： A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal.
摘要翻译：半导体器件具有分级位线结构，并且包括第一和第二本地位线，其传输与所选字线对应的第一和第二存储器单元的第一和第二信号，以及电连接到第一和第二本地的第一和第二全局位线通过第一和第二开关的位线，连接到第一和第二全局位线的第一和第二读出放大器以及控制电路。在同时访问第一和第二存储单元之后的第一时段期间，控制电路将第一开关控制到导通状态，使得第一读出放大器放大第一信号并将第二开关控制到非导通状态。在感测到第一读出放大器结束之后的第二周期期间，控制电路将第二开关控制到导通状态，使得第二读出放大器放大第二信号。

90. 发明授权

US08068369B2 Sense amplifier circuit and semiconductor memory device 有权
标题翻译：感应放大器电路和半导体存储器件
公开(公告)号：US08068369B2
公开(公告)日：2011-11-29
申请号：US12461858
申请日：2009-08-26
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C16/06
CPC分类号： G11C7/067 , G11C11/4091 , G11C11/4097
摘要： A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.
摘要翻译：单端读出放大器电路放大存储器单元的信号并通过位线传输，并且包括第一和第二MOS晶体管。第一MOS晶体管向位线提供预定电压，并且响应于控制电压控制位线和感测节点之间的连接，并且第二MOS晶体管具有连接到感测节点的栅极，并且放大从通过第一MOS晶体管的位线。在读取操作之前将预定电压提供给位线，并将其设置为使得可以在电荷转移模式之间的变化点附近获得存储单元的高电平和低电平数据之间的感测节点处的所需电压差以及在存储单元的读取电压范围内的电荷分配模式。

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