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81. 发明专利

JPH08320830A DATA PROCESSOR 失效
公开(公告)号：JPH08320830A
公开(公告)日：1996-12-03
申请号：JP24087195
申请日：1995-08-25
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , TAMAKI SANEAKI , NARITA SUSUMU
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： PURPOSE: To support plural page sizes without increasing chip occupation area or power consumption by allowing respective storage areas, where information on correspondence between logical page numbers and physical page numbers is stored, to be accessed with common index addresses. CONSTITUTION: A logical address space is divided into units called logical pages, and logical addresses are converted into physical addresses, page by page. A buffer memory 1 like an address conversion buffer is used in common to plural logical pages which are variable in size. A set associative cache memory which is equipped with a storage area for storing the correspondence information including a logical page number VPN and a physical page number PPN corresponding to it and has plural banks 11-14 accessed with the common index addresses 2 is used as the buffer memory 1.

82. 发明专利

JPH08320823A MICROPROCESSOR 失效
公开(公告)号：JPH08320823A
公开(公告)日：1996-12-03
申请号：JP26087395
申请日：1995-09-13
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , NARITA SUSUMU , NEMOTO MASATO
IPC分类号： G06F12/06 , G06F12/02 , G06F13/36
摘要： PURPOSE: To obtain good usability, decrease man-hours for the design of a personal computer, etc., and the number of external components, and reduce cost by providing an interface circuit which enables a semiconductor memory and a PC card to be coupled directly. CONSTITUTION: The personal computer includes a mother board MBD, mounted with a microprocessor MPU, as a basic configuration element. Two kinds of PC card, i.e., a memory card MEMC and an I/O card IOC are coupled with the mother board MBD through PC card slots PCSL1 and PCSL2, and a liquid crystal display LCD and a keyboard KBD being man-machine interfaces are coupled through connectors LCDCON and KBD ON. The microprocessor MPU operates in steps according to a program read out of a ROM or burst ROM to perform specific logical arithmetic processing and also control and supervise the respective parts of the personal computer.

83. 发明专利

JPH0831170A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0831170A
公开(公告)日：1996-02-02
申请号：JP18190094
申请日：1994-07-11
申请人： HITACHI LTD
发明人： MATSUI SHIGEZUMI , YOSHIOKA SHINICHI , YAMAMOTO MITSUTAKE , KAWASAKI IKUYA , NARITA SUSUMU , KANEKO SUSUMU
IPC分类号： G11C11/406 , G06F12/00
摘要： PURPOSE:To obtain a semiconductor integrated circuit device capable of reducing the power consumption of a dynamic RAM and capable of making the data processings of a microprocessor efficient. CONSTITUTION:This device has a storage bit corresponding to the refreshing address of the dynamic RAM and also a refreshing address counter generating a refreshing address by a refreshing starting signal made to be corresponded to the refreshing cycle of the dynamic RAM and performs the recording of a memory access when the memory access is performed to the storage circuit. Then, the device reads out a storage bit corresponding to an address in which a refresh is to be performed by the refreshing starting signal and the refreshing address signal and when the recording of the memory access is present, the device allows only the refereshing address to be updated by making a refreshing control signal ineffective and also allows the recording to be cleared and besides when the recording of the memory access is not present, the device allows a refreshing operation to be performed in the address.

84. 发明专利

JPH0830351A MICROPROCESSOR 失效
公开(公告)号：JPH0830351A
公开(公告)日：1996-02-02
申请号：JP18190194
申请日：1994-07-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUI SHIGEZUMI , YAMAMOTO MITSUTAKE , YOSHIOKA SHINICHI , NARITA SUSUMU , KAWASAKI IKUYA , KANEKO SUSUMU , HASEGAWA KIYOSHI
IPC分类号： G06F15/78 , G06F1/06 , G11C11/407
摘要： PURPOSE:To switch a system clock at high speed by forming an oscillating pulse by multiplying the pulse of a low frequency while using a PLL circuit, and outputting the clock corresponding to a low-speed/high-speed mode and the stability degree of a circuit. CONSTITUTION:At a clock pulse generating circuit built in the microprocessor, an oscillation circuit XOSC forms the oscillating pulse of the comparatively low frequency corresponding to the low-speed operating mode and the PLL circuit multiplies this pulse as a reference frequency signal so that two kinds of clock pulses DV1 and DV2 for the high-speed operating mode can be formed. When the microprocessor is set in the low-speed operating mode, clock pulses CK1 and CK2 of the comparatively low frequency are outputted and when any event requiring a high-speed operation is generated, multiplexers MUX 3 and MUX 4 continuously output the clock pulses for low speed until the PLL circuit is turned to an operating state and stabilized but when the PLL circuit is stabilized, clock pulses for a high-speed operation are outputted.

85. 发明专利

JPH04199244A CACHE METHOD, CACHE DEVICE, AND ADDRESS ASSIGNING METHOD 失效
公开(公告)号：JPH04199244A
公开(公告)日：1992-07-20
申请号：JP31782490
申请日：1990-11-26
申请人： HITACHI LTD , HITACHI KEIYO ENG
发明人： HIUGA NOBUO , UMINAGA MASAHIRO , TAKAGI KATSUAKI , KAWASAKI IKUYA , MATSUI SHIGESUMI
IPC分类号： G06F12/08 , G06F12/10
摘要： PURPOSE:To increase the effect of a cache memory and make the executing speed faster by making registration in cache memories by distinguishing arrays between a big one and others. CONSTITUTION:A higher-order address inspector 101 and signal lines 102 and 103 are added so that whether or not the bit pattern of the higher-order bit field of an address is a prefixed pattern can be inspected and, depending upon the results of the inspection, caching is made to different memories. Accordingly, the action to a cache memory can be changed between the access to the data in a big array and the access to other data and the content of an ordinary area 401 in a cache memory is not affected and not forced to go out even when a big array arranging area 402 is accessed. Therefore, the executing speed is improved.

86. 发明专利

JPH02195431A ADDRESS OPERATION CONTROL DEVICE 失效
公开(公告)号：JPH02195431A
公开(公告)日：1990-08-02
申请号：JP1397689
申请日：1989-01-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KUBO MITSUYUKI , KAWASAKI IKUYA , HASEGAWA ATSUSHI
IPC分类号： G06F9/355 , G06F12/04
摘要： PURPOSE:To prevent the execution time of a bit operating instruction from being increased by controlling the substitution of a prescribed bit for the lower bit side of an access address so that the operand of a specified size does not exceed the word boundary of a memory in accordance with the access address and the specified data size information of the operand. CONSTITUTION:A base address BA for specifying data obtained by setting up the set of plural bits as a minimum unit is inputted from an input circuit 2 to one input terminal of an adder 1 in an address operation control device and an OFFSET for applying the bit operating position of data based upon the base address BA is applied to the other input terminal through an input circuit 3 and a shift circuit 4. The adder 1 forms the access address AA of data including a bit to be operated by using the OFFSET and the lower bits and upper bits are respectively inputted to a selector 5 and an output circuit 6. The prescribed bit is substituted for the lower bit side of the access address AA by a selector 5 so that the operand does not exceed the word boundary of the memory and controlled by a substitution control unit 12.

87. 发明专利

JPH0293716A CLOCK PULSE GENERATOR WITH FUNCTION FOR OUTPUTTING CLOCK SYNCHRONOUS RESET SIGNAL 失效
公开(公告)号：JPH0293716A
公开(公告)日：1990-04-04
申请号：JP24418788
申请日：1988-09-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KAWASAKI IKUYA , HASEGAWA ATSUSHI
IPC分类号： G06F1/24 , G06F1/00
摘要： PURPOSE:To execute the phase matching of a constituting element without a hardware excepting for a clock pulse generator (CPG) even at the time of resetting power-on by generating a reset signal when a signal to show the stability of a power source voltage is inputted to a CPG circuit. CONSTITUTION:At the time of resetting power-on, a reset input signal 3 is an L level and respective constituting elements 5 are in a reset condition. Then, the phase of an internal clock is dissident. When a power source is enough stable and the signal to show the stability of the power source is inputted to the CPG, the CPG detects this signal and a reset output signal 2 is forcibly caused to be an H level for a constant period regardless of the level of the reset input signal 3. After that, the reset output signal 2 is caused to be the L level. This transient timing is synchronized to a clock 1 and the respective system constituting elements 5 can match the phase of the internal clock samely as the time of normal reset. After that, when the signal is changed from the L level to the H level, the signal 2 is changed from the L level to the H level synchronously with the clock 1 and the respective elements 5 start operation.

88. 发明专利

JPH01134636A DATA PROCESSING DEVICE 失效
公开(公告)号：JPH01134636A
公开(公告)日：1989-05-26
申请号：JP29380987
申请日：1987-11-20
申请人： HITACHI LTD
发明人： MASUDA SATOSHI , KAWASAKI IKUYA , MATSUI SHIGESUMI
IPC分类号： G06F11/28 , G06F11/26 , G06F11/34 , G06F11/36 , G06F12/08 , G06F12/10 , G06F15/78
摘要： PURPOSE:To easily reversely convert the information given to an external part and to obtain internal information by outputting an instructing signal to instruct the access timing to the external part when the converting information is set to a converting table. CONSTITUTION:When a main memory 10 is accessed and converting information is set to an address converting buffer 8, a memory control unit 7 outputs an instructing signal phi to instruct the access timing of the memory 10 to an external part. The signal phi is supplied to an emulator main body 20. The main body 20 stores the address, the data, the signal phi and respective types of control signals into a first trace memory 21A of a trace memory part 21. Further, the information of an address bus AB and a data bus DB is fetched even into a second trace memory 21b. The main body 20 is equipped with an address reverse converting table 22 to convert reversely a physical address to a logical address. The table 22 is used to convert the physical address to the logical address.

89. 发明专利

JPS6467674A MICROPROCESSOR SYSTEM 失效
公开(公告)号：JPS6467674A
公开(公告)日：1989-03-14
申请号：JP22395887
申请日：1987-09-09
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HASHIMOTO KOJI , HASEGAWA ATSUSHI , KAWASAKI IKUYA , IWASAKI KAZUHIKO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To prevent data transferring efficiency from being lowered by supplying information, which show a data storing position to be a data transferring source or a data transferring destination, to a co-processor, causing the co- processor to be independent together with a main processor and supervising the number of a series of data transferrings or the end of a series of data transferring operation. CONSTITUTION:A main processor 1 stores the number of data transferring to be needed for access control to the data transferring. For a co-processor 2, since a resistor to be supplied for the data transferring is designated by a command and a parameter supplied from the main processor 1, the exchange of information besides it is not needed and the data transferring operation is executed. Thus, the decreasing of an over-head between the main processor 1 and the co-processor 2 in such data transferring operation can be achieved.

90. 发明专利

JPS6435647A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6435647A
公开(公告)日：1989-02-06
申请号：JP19008087
申请日：1987-07-31
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI ENG CO LTD
发明人： IWASAKI KAZUHIKO , KAWASAKI IKUYA , FUNABASHI TSUNEO , INAYOSHI HIDEO , HASEGAWA ATSUSHI , YAGINUMA TAKAO , KONDO EIKI
IPC分类号： G06F9/38 , G06F15/16
摘要： PURPOSE:To enable transfer between a memory and a CP through one bus cycle by adding a coprocessor space signal (CPS) and a coprocessor cycle signal (CPCYCL) or a command transfer cycle signal (AT2-0) to a coprocessor in addition to an ordinary memory access signal of a microprocessor. CONSTITUTION:When the microprocessor MPU1 fetches an instruction, which a coprocessor CP should process, it transmits an instruction CPS corresponding to this to the CP. At such a time, it transmits the AT2-0, showing that is is the bus cycle to transfer the instruction to the CP as well to the CP together with the instruction. In case of an operand is transferred from the memory 3 to the CP, the MPU1 asserts the signal CPYCL, showing the effectiveness of CP data in addition to the signal of ordinary memory read, and instructs the CP to fetch the data, and performs the transfer between the memory and the CP. In case of the data is transferred from the CP to the memory, the MPU asserts the CPCYCL signal, and instructs the CP to output the data to perform the transfer.

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