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1. 发明专利

JPS62214464A COPROCESSOR COUPLING SYSTEM 失效
公开(公告)号：JPS62214464A
公开(公告)日：1987-09-21
申请号：JP5684486
申请日：1986-03-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI ENG CO LTD
发明人： IWASAKI KAZUHIKO , FUNABASHI TSUNEO , KAWASAKI IKUYA , INAYOSHI HIDEO , HASEGAWA ATSUSHI , YAGINUMA TAKAO , KONDO EIKI
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167
摘要： PURPOSE:To transfer data between a memory and a coprocessor CP in one bus cycle by adding CPS and CPCYCL pins besides memory access signal pins of a microprocessor to select the CP simultaneously with memory access. CONSTITUTION:When an operand is transferred from a memory 3 to a CP 2, a microprocessor (MPU) 1 asserts not only a memory read signal but also a signal (CPCYCL) indicating the validity of coprocessor data and instructs the CP 2 to take in data, and the operand is transferred from the memory to the CP in one bus cycle. When data is transferred from the CP 2 to the memory 3, the MPU 1 asserts not only a memory write signal but also the signal (CPCYCL) and instructs the CP 2 to output data, and the data is transferred from the CP 2 to the memory 3 in one bus cycle.

2. 发明专利

JPS6435647A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6435647A
公开(公告)日：1989-02-06
申请号：JP19008087
申请日：1987-07-31
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI ENG CO LTD
发明人： IWASAKI KAZUHIKO , KAWASAKI IKUYA , FUNABASHI TSUNEO , INAYOSHI HIDEO , HASEGAWA ATSUSHI , YAGINUMA TAKAO , KONDO EIKI
IPC分类号： G06F9/38 , G06F15/16
摘要： PURPOSE:To enable transfer between a memory and a CP through one bus cycle by adding a coprocessor space signal (CPS) and a coprocessor cycle signal (CPCYCL) or a command transfer cycle signal (AT2-0) to a coprocessor in addition to an ordinary memory access signal of a microprocessor. CONSTITUTION:When the microprocessor MPU1 fetches an instruction, which a coprocessor CP should process, it transmits an instruction CPS corresponding to this to the CP. At such a time, it transmits the AT2-0, showing that is is the bus cycle to transfer the instruction to the CP as well to the CP together with the instruction. In case of an operand is transferred from the memory 3 to the CP, the MPU1 asserts the signal CPYCL, showing the effectiveness of CP data in addition to the signal of ordinary memory read, and instructs the CP to fetch the data, and performs the transfer between the memory and the CP. In case of the data is transferred from the CP to the memory, the MPU asserts the CPCYCL signal, and instructs the CP to output the data to perform the transfer.

3. 发明专利

JPS6383851A SYSTEM FOR DISCRIMINATING INPUT/OUTPUT DATA 失效
公开(公告)号：JPS6383851A
公开(公告)日：1988-04-14
申请号：JP22818586
申请日：1986-09-29
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IWASAKI KAZUHIKO , AOKI HIROKAZU , KAWASAKI IKUYA , HASEGAWA ATSUSHI , FUNABASHI TSUNEO
IPC分类号： G06F13/42 , G06F15/78
摘要： PURPOSE:To omit the external circuits and to increase the data access speed by using plural input pins for data complete signals and producing an OR within a microprocessor. CONSTITUTION:The inverse of DC0 input signal is supplied to test machine 21 via an inverter 28, a NOR gate 29 and an inverter 30, while the inverse of DC1 input signal is supplied to the machine 21 via an inverter 32, the gate 29 and the inverter 30 respectively. For the input signal of a microprocessor, plural inverters are generally cascaded at the stages following an input pad. These inverters are replaced with NOR and an OR is secured. The circuit delay due to the cascade of inverters and the circuit delay caused when the circuit delay serves as a NOR by an amount equal to a stage are very small in a CMOS process. Thus it is not required to produce an OR through an external circuit, therefore, the data access speed is increased.

4. 发明专利

JPH0578863B2 失效
公开(公告)号：JPH0578863B2
公开(公告)日：1993-10-29
申请号：JP5684486
申请日：1986-03-17
申请人： HITACHI LTD , HITACHI MICRO SYSTEM KK , HITACHI ENG CO LTD
发明人： IWASAKI KAZUHIKO , FUNABASHI TSUNEO , KAWASAKI IKUYA , INAYOSHI HIDEO , HASEGAWA ATSUSHI , YAGINUMA TAKAO , KONDO EIKI
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167

5. 发明授权

KR840001223B1 래치회로가 부착된 시프트 레지스터 失效
公开(公告)号：KR840001223B1
公开(公告)日：1984-08-21
申请号：KR800001835
申请日：1980-05-09
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , FUNABASHI TSUNEO
IPC分类号： G11C19/28

6. 发明专利

DE3370702D1 MICROCOMPUTER SYSTEM WITH BUFFER IN PERIPHERAL STORAGE CONTROL 未知
公开(公告)号：DE3370702D1
公开(公告)日：1987-05-07
申请号：DE3370702
申请日：1983-03-07
申请人： HITACHI LTD
发明人： FUNABASHI TSUNEO , IWASAKI KAZUHIKO , NAKAMURA HIDEO
IPC分类号： G06F3/06 , G06F13/00 , G06F13/28
摘要： Herein disclosed is a microcomputer system having a peripheral storage control (107) equipped with both a circuit made responsive to a transfer command given from an MPU (101) to set a transfer start address, which is designated subsequent to that command, in a counter (111), which is made operative to give an address for a buffer (110), and to transfer the output of the buffer (110) to a common bus (112) connected between the MPU (101) and an RAM (102), and a circuit (103) for controlling the aforementioned counter (111) to count up in response to a transfer acknowledge signal which is subsequently fed from a direct memory access control (106). In order that the date in the buffer (110) may not be transferred to the RAM (102) but the rewritten, the peripheral storage control (103) is further equipped with both a circuit for setting a rewrite address further given from the MPU (101) in the counter (111) which is operative to give the address of the buffer (110), in association with a rewrite command fed from the MPU (101), and a circuit for giving the rewrite signal to the buffer (110) each time the rewrite data are given after the setting operation from the MPU (101).

7. 发明专利

DE3018509A1 未知
公开(公告)号：DE3018509A1
公开(公告)日：1980-11-20
申请号：DE3018509
申请日：1980-05-14
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , FUNABASHI TSUNEO
IPC分类号： G11C19/18 , G11C19/28

8. 发明专利

DE3855284T2 未知
公开(公告)号：DE3855284T2
公开(公告)日：1996-12-05
申请号：DE3855284
申请日：1988-01-08
申请人： HITACHI LTD
发明人： FUNABASHI TSUNEO , SAKOSHITA KAORU , YONEZAWA HIROSHI
IPC分类号： G06F15/167 , G06F13/28 , G06F15/17 , G06F15/16
摘要： A multi-microcomputer system comprising a first microcomputer system, a second microcomputer system, and a direct memory access controller which has a function of controlling a data transfer operation that is executed between the first microcomputer system and the second microcomputer system.

9. 发明专利

DE3033867A1 未知
公开(公告)号：DE3033867A1
公开(公告)日：1981-04-09
申请号：DE3033867
申请日：1980-09-09
申请人： HITACHI LTD
发明人： NAKAMURA HIDEO , FUNABASHI TSUNEO , KOIZUMI HARUO
IPC分类号： G06F7/68 , H03K5/00 , H03K5/156
摘要： In a pulse frequency multiplying circuit, a first capacitor charged to a given potential is discharged through a first constant-current circuit during a period corresponding to a pulse width of a reference pulse. Then, the terminal voltage of the first capacitor is applied as a reference voltage to one input terminal of a comparator circuit. A triangle wave voltage formed by alternately discharging a pair of second capacitors charged to a given potential, through a second constant-current circuit with a current value n times that in the first constant-current circuit, is applied to the other input terminal of the comparator circuit. The output from the comparator circuit operates a flip-flop circuit. In accordance with the output signal, the charge/discharge operation of said second capacitors is switched, whereby said flip-flop circuit produces a pulse with a frequency n times that of the reference pulse.

10. 发明专利

DE3270103D1 INSULATED GATE FIELD EFFECT TRANSISTOR 未知
公开(公告)号：DE3270103D1
公开(公告)日：1986-04-30
申请号：DE3270103
申请日：1982-07-22
申请人： HITACHI LTD
发明人： SAKAI YOSHIO , FUNABASHI TSUNEO
IPC分类号： H01L21/82 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/78
摘要： An insulated gate field transistor has a well region (42) formed in a semiconductor substrate (41) of different conductivity type. The well region (42) has an opening in it so that a part of the substrate (47) extends within it. Source and drain regions (43, 44) are formed in the well region (42) on opposite sides of the opening, with the same conductivity type as the substrate (41). An insulating layer (45) is formed on the surface of the substrate between the source and drain regions (43, 44) and a gate electrode (46) is formed on the insulating layer (45). A potential is applied to the gate electrode (46) to reverse-bias the substrate-well junction and a depletion layer (48) is formed which includes the part of the substrate (41) between the source and drain regions (43, 44). This enables the transistor to have a small body effect, so that it maybe operated with a constant current charac.

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