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1. 发明专利

DE69943120D1 Integrierte Halbleiterschaltung 未知
公开(公告)号：DE69943120D1
公开(公告)日：2011-02-24
申请号：DE69943120
申请日：1999-09-06
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , NARITA SUSUMU
IPC分类号： G11C5/14 , H03K19/00 , G01R31/30

2. 发明专利

DE69529374T2 未知
公开(公告)号：DE69529374T2
公开(公告)日：2003-10-23
申请号：DE69529374
申请日：1995-09-11
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

3. 发明专利

MY130260A SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS 未知
公开(公告)号：MY130260A
公开(公告)日：2007-06-29
申请号：MYPI9903881
申请日：1999-09-08
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , NARITA SUSUMU
IPC分类号： G11C5/14 , H03K19/00 , H03K3/01
摘要： A SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDES A FIRST CONTROLLED CIRCUIT (100) HAVING AT UNIT (102) FOR GENERATING A SUBSTRATE BIAS VOLTAGE OF THE MOS TRANSISTOR,WHEREIN WHEN THE SUBSTRATE BIAS CONTROL UNIT (102) IS SET IN A FIRST MODE, A COMPARATIVELY LARGE CURRENT IS ALLOWED TO FLOW BETWEEN THE SOURCE AND DRAIN OF THE MOS TRANSISTOR, WHILE WHEN THE SUSBTRATE BIAS CONTROL UNIT (102) IS SET IN A SECOND MODE,THE COMPARATIVELY LARGE CURRENT ALLOWED TO FLOW BETWEEN THE SOURCE AND DRAIN PF THE MOS TRANSISTOR IS CONTROLLED TO A CURRENT OF SMALLER VALUE. THE VALUE OF THE SUBSTRATE BIAS APPLIED TO THE FIRST CONTROLLED CIRCUIT IS LARGER IN THE SECOND MODE THAN IN THE FIRST MODE FOR THE SUBSTRATE BIAS OF THE PMOS TRANSISTOR, AND SMALLER IN THE SECOND MODE THAN IN THE FIRST MODE FOR THE SUBSTRATE BIAS OF THE NMOS TRANSISTOR.THE POWER SUPPLY VOLTAGE APPLIED TO THE FIRST CONTROLLED CIRCUIT (100) IS CONTROLLED TO A SMALLER VALUE IN THE SECOND MODE THAN IN THE FIRST MODE.(FIG 1A & 1B)

4. 发明专利

DE69133134D1 未知
公开(公告)号：DE69133134D1
公开(公告)日：2002-11-21
申请号：DE69133134
申请日：1991-07-03
申请人： HITACHI LTD
发明人： NARITA SUSUMU , ARAKAWA FUMIO , OKADA TETSUHIKO , UCHIYAMA KUNIO
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F12/04
摘要： An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder ID0, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.

5. 发明专利

SG125053A1 Semiconductor integrated circuit apparatus 未知
公开(公告)号：SG125053A1
公开(公告)日：2006-09-29
申请号：SG200104041
申请日：1999-09-08
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , NARITA SUSUMU
IPC分类号： G11C5/14 , G01R31/00 , H01L21/00 , H03K19/00
摘要： A semiconductor integrated circuit apparatus includes a first controlled circuit (100) having at least one MOS transistor and a substrate bias control unit (102) for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit (102) is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit (102) is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.

6. 发明专利

DE69529374D1 未知
公开(公告)号：DE69529374D1
公开(公告)日：2003-02-20
申请号：DE69529374
申请日：1995-09-11
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

7. 发明专利

DE69520718T2 未知
公开(公告)号：DE69520718T2
公开(公告)日：2001-08-02
申请号：DE69520718
申请日：1995-09-01
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

8. 发明专利

DE69520718D1 未知
公开(公告)号：DE69520718D1
公开(公告)日：2001-05-23
申请号：DE69520718
申请日：1995-09-01
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

9. 发明专利

DE3853985T2 未知
公开(公告)号：DE3853985T2
公开(公告)日：1996-02-22
申请号：DE3853985
申请日：1988-12-22
申请人： HITACHI LTD
发明人： NARITA SUSUMU , HANAWA MAKOTO , NISHIMUKAI TADAHIKO , OKADA TETSUHIKO
IPC分类号： G06F9/26
摘要： Herein disclosed is a data processing apparatus (100) such as a pipeline processing microprocessor, in which the content of a subsequent instruction to be fetched from a memory is different depending upon the formation or non-formation of a conditional branch instruction. In order to execute the conditional branch instruction, a micro-ROM contains: a first micro-instruction having an information for a conditional discrimination, an information requesting a branch ready and a subsequent micro-address of an even address; a second micro-instruction having an information requesting a branch and a subsequent micro-address of an odd address; and a third micro-instruction requesting a subsequent instruction decoding. When the branch condition is formed, the even address is outputted from a micro-address generating circuit (115). Before the branch is requested by the second micro-instruction, a micro-address analyzing circuit (130) feeds, if the brach condition is formed, the branch request signal to an instruction fetch unit (101) in response to the even address and the branch ready information of the first micro-instruction so that the time interval between the execution of the conditional branch instruction and the execution of the subsequent instruction can be shortened.

10. 发明专利

DE3853985D1 未知
公开(公告)号：DE3853985D1
公开(公告)日：1995-07-20
申请号：DE3853985
申请日：1988-12-22
申请人： HITACHI LTD
发明人： NARITA SUSUMU , HANAWA MAKOTO , NISHIMUKAI TADAHIKO , OKADA TETSUHIKO
IPC分类号： G06F9/26
摘要： Herein disclosed is a data processing apparatus (100) such as a pipeline processing microprocessor, in which the content of a subsequent instruction to be fetched from a memory is different depending upon the formation or non-formation of a conditional branch instruction. In order to execute the conditional branch instruction, a micro-ROM contains: a first micro-instruction having an information for a conditional discrimination, an information requesting a branch ready and a subsequent micro-address of an even address; a second micro-instruction having an information requesting a branch and a subsequent micro-address of an odd address; and a third micro-instruction requesting a subsequent instruction decoding. When the branch condition is formed, the even address is outputted from a micro-address generating circuit (115). Before the branch is requested by the second micro-instruction, a micro-address analyzing circuit (130) feeds, if the brach condition is formed, the branch request signal to an instruction fetch unit (101) in response to the even address and the branch ready information of the first micro-instruction so that the time interval between the execution of the conditional branch instruction and the execution of the subsequent instruction can be shortened.

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