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1. 发明专利

JPH0417046A ADDRESS CONVERTER 失效
公开(公告)号：JPH0417046A
公开(公告)日：1992-01-21
申请号：JP11984690
申请日：1990-05-11
申请人： HITACHI LTD , HITACHI KEIYO ENG
发明人： UMINAGA MASAHIRO , HIUGA NOBUO , KAWASAKI IKUYA , TAKAGI KATSUAKI , AKITA HIDEHIKO
IPC分类号： G06F12/10
摘要： PURPOSE:To prevent the decline of the address converting speed of an address converter at the time of increasing the address width by providing a buffer memory which stores the correlation between the higher rank section of an inputted logical address and the base address of an intermediate stage table. CONSTITUTION:A buffer memory 109 is provided and the correlation between an inputted logical address and the base address of an intermediate stage of a conversion table is stored in the memory 109. The registration in this memory 19 is made based on a TLB 113. Namely, the table base of an intermediate stage obtained in the stage where a physical address is found from a logical address is stored in the memory 109. Therefore, when the inputted logical address is registered in the buffer memory 109, the base address of the intermediate stage of the conversion table can be found immediately even when the inputted logical address is not registered in the TLB 113. Therefore, the converting speed of this address converter is increased, since the access to the table from the initial stage to the intermediate stage can be omitted and the time required for making address conversion can be reduced by the omitted accessing time.

2. 发明专利

JPS6325736A INTERRUPTION CONTROL SYSTEM FOR VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS6325736A
公开(公告)日：1988-02-03
申请号：JP16799586
申请日：1986-07-18
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI KEIYO ENG
发明人： TAKENOYA YOSHIAKI , TSUTSUI SHIGECHIKA , MIURA AKIYOSHI , UMENO HIDENORI , NISHIMUKAI TADAHIKO , KAWASAKI IKUYA
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To simplify program processing by using a register which holds the holding state of each level of the interruptions given to an operating system (OS) and calculating those interruption levels and their holding states to a control program from the contents of said register. CONSTITUTION:An IPL register provided to the hardware holds the holding state of each level of interruptions. In a flow of a microprogram which executes a privilege instruction via a VM, it is first decided whether or not an interrupting mask level is changed by an instruction which controls a status register. Then it is checked whether the mask level is reduced or not compared with the previous level when said interruption mask level is changed. If so, the reference is given to the IPL register. Then the calculation is carried out to a VMM when it is confirmed that a holding interruption exists at a level higher than that set after a change with reference to the interruption holding state of each level.

3. 发明专利

JPH04199244A CACHE METHOD, CACHE DEVICE, AND ADDRESS ASSIGNING METHOD 失效
公开(公告)号：JPH04199244A
公开(公告)日：1992-07-20
申请号：JP31782490
申请日：1990-11-26
申请人： HITACHI LTD , HITACHI KEIYO ENG
发明人： HIUGA NOBUO , UMINAGA MASAHIRO , TAKAGI KATSUAKI , KAWASAKI IKUYA , MATSUI SHIGESUMI
IPC分类号： G06F12/08 , G06F12/10
摘要： PURPOSE:To increase the effect of a cache memory and make the executing speed faster by making registration in cache memories by distinguishing arrays between a big one and others. CONSTITUTION:A higher-order address inspector 101 and signal lines 102 and 103 are added so that whether or not the bit pattern of the higher-order bit field of an address is a prefixed pattern can be inspected and, depending upon the results of the inspection, caching is made to different memories. Accordingly, the action to a cache memory can be changed between the access to the data in a big array and the access to other data and the content of an ordinary area 401 in a cache memory is not affected and not forced to go out even when a big array arranging area 402 is accessed. Therefore, the executing speed is improved.

4. 发明专利

DE3751758D1 未知
公开(公告)号：DE3751758D1
公开(公告)日：1996-05-02
申请号：DE3751758
申请日：1987-08-27
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , SAKAMURA KEN
发明人： SAKAMURA KEN , KAWASAKI IKUYA , HASEGAWA ATSUSHI , IWASAKI KAZUHIKO , TONOMURA MOTONOBU
IPC分类号： G06F9/305 , G06F7/00 , G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34
摘要： A microprocessor is disclosed which includes instruction decoding means (4), instruction execution means (6) and information holding means (3), and includes a first step of storing the information obtained by execution of a first instruction in the information holding means (3) and a second step of controlling the instruction execution means on the basis of the information when a second instruction is executed.

5. 发明专利

DE3750284T2 未知
公开(公告)号：DE3750284T2
公开(公告)日：1994-11-17
申请号：DE3750284
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： HASHIMOTO KOUZI , HASEGAWA ATSUSHI , KAWASAKI IKUYA , IWASAKI KAZUHIKO
IPC分类号： G06F15/16 , G06F9/312 , G06F9/38 , G06F15/177
摘要： When the coprocessor communicates a plurality of data items with the master processor and the memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with an information indicating a data storage position as a data transfer source or destination, and the master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto and further is not required to indicate the end of the sequence of data transfer cycles to the master processor.

6. 发明专利

DE3750284D1 未知
公开(公告)号：DE3750284D1
公开(公告)日：1994-09-01
申请号：DE3750284
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： HASHIMOTO KOUZI , HASEGAWA ATSUSHI , KAWASAKI IKUYA , IWASAKI KAZUHIKO
IPC分类号： G06F15/16 , G06F9/312 , G06F9/38 , G06F15/177
摘要： When the coprocessor communicates a plurality of data items with the master processor and the memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with an information indicating a data storage position as a data transfer source or destination, and the master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto and further is not required to indicate the end of the sequence of data transfer cycles to the master processor.

7. 发明专利

DE69127992D1 未知
公开(公告)号：DE69127992D1
公开(公告)日：1997-11-27
申请号：DE69127992
申请日：1991-04-17
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： MATSUI SHIGEZUMI , KAWASAKI IKUYA , KONDO YOSHIYUKI , HASHIMOTO KOUJI
IPC分类号： G06F11/26 , G06F11/34 , G06F11/36 , G06F11/00
摘要： A microprocessor having a buffer (10) or memory capable of holding a plurality of instructions in advance has a function to permitting the insertion of a special bus cycle for outputting the internal information of the microprocessor externally of the microprocessor in a predetermined operation mode at the time of each execution. The information inside the microprocessor, which is to be outputted to the exterior in the special bus cycle, is exemplified by the address of the executed instruction in a memory space, an instruction code or the code for identifying said executed instruction in the instruction group prefetched. In the emulation of the system using the instruction prefetch type microprocessor, according to the means described above, the instruction that has been executed can be easily known from the exterior so that an accurate emulation analysis is possible and facilitating the analysis of the trace data thereby to improve the debugging efficiency.

8. 发明专利

DE3750662D1 未知
公开(公告)号：DE3750662D1
公开(公告)日：1994-11-17
申请号：DE3750662
申请日：1987-06-30
申请人： HITACHI LTD
发明人： HANAWA MAKOTO , KAWASAKI IKUYA , NISHIMUKAI TADAHIKO
IPC分类号： G06F13/00 , G06F11/14
摘要： A microprocessor (100) and a peripheral equipment communicate data through a bus (140). If an error occurs during the communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, and if an address signal corresponds to access to an unmounted area of the peripheral equipment or an area of an I/O equipment, the microprocessor inhibits the retry.

9. 发明专利

DE69529374T2 未知
公开(公告)号：DE69529374T2
公开(公告)日：2003-10-23
申请号：DE69529374
申请日：1995-09-11
申请人： HITACHI LTD
发明人： YOSHIOKA SHINICHI , KAWASAKI IKUYA , NARITA SUSUMU , TAMAKI SANEAKI
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12 , G06F12/14 , G11C29/24
摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

10. 发明专利

DE3751758T2 未知
公开(公告)号：DE3751758T2
公开(公告)日：1996-11-07
申请号：DE3751758
申请日：1987-08-27
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , SAKAMURA KEN
发明人： SAKAMURA KEN , KAWASAKI IKUYA , HASEGAWA ATSUSHI , IWASAKI KAZUHIKO , TONOMURA MOTONOBU
IPC分类号： G06F9/305 , G06F7/00 , G06F9/30 , G06F9/308 , G06F9/318 , G06F9/34
摘要： A microprocessor is disclosed which includes instruction decoding means (4), instruction execution means (6) and information holding means (3), and includes a first step of storing the information obtained by execution of a first instruction in the information holding means (3) and a second step of controlling the instruction execution means on the basis of the information when a second instruction is executed.

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