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81. 发明授权

US06320215B1 Crystal-axis-aligned vertical side wall device 有权
标题翻译：水晶轴对齐垂直侧壁装置
公开(公告)号：US06320215B1
公开(公告)日：2001-11-20
申请号：US09359292
申请日：1999-07-22
申请人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Gary Bronner , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译：一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件在侧壁上的刻面晶体区域上。小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

82. 发明授权

US06268638B1 Metal wire fuse structure with cavity 失效
标题翻译：金属线熔丝结构带腔
公开(公告)号：US06268638B1
公开(公告)日：2001-07-31
申请号：US09258563
申请日：1999-02-26
申请人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
发明人： Axel C. Brintzinger , Edward W. Kiewra , Chandrasekhar Narayan , Carl J. Radens
IPC分类号： H01L2702
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译：集成电路具有初级器件，并且冗余器件通过至少一个熔丝被选择性地代替初级器件。熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。

83. 发明授权

US06174762B1 Salicide device with borderless contact 失效
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06174762B1
公开(公告)日：2001-01-16
申请号：US09260311
申请日：1999-03-02
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

84. 发明授权

US6165864A Tapered electrode for stacked capacitors 失效
标题翻译：用于堆叠电容器的锥形电极
公开(公告)号：US6165864A
公开(公告)日：2000-12-26
申请号：US123298
申请日：1998-07-28
申请人： Hua Shen , Joachim Nuetzel , Carl J. Radens , David Kotecki
发明人： Hua Shen , Joachim Nuetzel , Carl J. Radens , David Kotecki
IPC分类号： H01G4/12 , H01L21/02 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/82
摘要： A method for forming a stacked capacitor includes the steps of providing a first insulating layer having a conductive access path therethrough, forming a second insulating layer on the first insulating layer, forming a trench in the second insulating layer, the trench having tapered sidewalls, forming a first electrode in the trench and on the trench sidewalls, the first electrode being electrically coupled to the conductive access path, forming a dielectric layer on the first electrode and forming a second electrode on the dielectric layer. A stacked capacitor having increased surface area includes a first electrode formed in a trench provided in a dielectric material. The first electrode has tapered surfaces forming a conically shaped portion of the first electrode, the first electrode for accessing a capacitively coupled storage node.
摘要翻译：一种叠层电容器的形成方法包括以下步骤：提供具有导电通路的第一绝缘层，在第一绝缘层上形成第二绝缘层，在第二绝缘层中形成沟槽，沟槽具有锥形侧壁，形成所述沟槽中的第一电极和所述沟槽侧壁上的第一电极，所述第一电极电耦合到所述导电接入路径，在所述第一电极上形成电介质层，并在所述电介质层上形成第二电极。具有增加的表面积的堆叠电容器包括形成在设置在电介质材料中的沟槽中的第一电极。第一电极具有形成第一电极的锥形部分的锥形表面，用于访问电容耦合存储节点的第一电极。

85. 发明申请

US20130334618A1 METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION 有权
标题翻译：金属氧化物半导体场效应晶体管（MOSFET）栅极终止
公开(公告)号：US20130334618A1
公开(公告)日：2013-12-19
申请号：US13495081
申请日：2012-06-13
申请人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
发明人： Christopher V. Baiocco , Daniel J. Jaeger , Carl J. Radens , Helen Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L21/28247 , H01L29/0642 , H01L29/0649 , H01L29/51 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.
摘要翻译：提供一种形成半导体器件的方法，其包括在半导体衬底中形成含有隔离区的氧化物以限定有源半导体区域。然后可以在有源半导体区域上形成包括高k栅极电介质层的覆盖栅极堆叠。覆盖栅极堆叠的至少一部分从有源半导体器件区域延伸到隔离区域。然后可以对覆盖栅极堆叠进行蚀刻以在隔离区域上提供开口。然后可以对由开口暴露的隔离区域的表面进行各向同性蚀刻，以在隔离区域内形成在高k栅极电介质层下延伸的底切区域。然后可以在填充底切区域的开口中形成密封电介质材料。然后可以对覆盖栅极堆叠进行构图以形成栅极结构。

86. 发明授权

US08486511B2 Pattern formation employing self-assembled material 有权
标题翻译：采用自组装材料的图案形成
公开(公告)号：US08486511B2
公开(公告)日：2013-07-16
申请号：US13430177
申请日：2012-03-26
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
IPC分类号： B32B3/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
摘要翻译：在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。

87. 发明申请

US20130077415A1 CIRCUIT FOR MEMORY CELL RECOVERY 失效
标题翻译：用于记忆细胞恢复的电路
公开(公告)号：US20130077415A1
公开(公告)日：2013-03-28
申请号：US13247362
申请日：2011-09-28
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Carl J. Radens
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/04 , G11C11/417 , G11C11/419
摘要： An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.
摘要翻译：一种用于抵抗存储单元中偏置温度不稳定性（BTI）的影响的装置和方法。连接到存储器单元的位线包含两个交替的交替路径，以将第一位线的下部连接到第二位线的上部，并且将第二位线的下部连接到第二位线的上部第一个位线。在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对的位线读取和写入存储器单元。存储器单元可以通过位线读取到读出放大器，位线上的晶体管随后被去激活，并且激活交替路径上的晶体管以将转置的位值写入存储器单元，从而反转偏置。

88. 发明授权

US08299455B2 Semiconductor structures having improved contact resistance 有权
标题翻译：具有改善的接触电阻的半导体结构
公开(公告)号：US08299455B2
公开(公告)日：2012-10-30
申请号：US11872291
申请日：2007-10-15
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L29/06
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译：自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。接触电阻的降低又改善了通过结构的电流的流动。除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

89. 发明申请

US20120126937A1 ASSET MANAGEMENT INFRASTRUCTURE 有权
标题翻译：资产管理基础设施
公开(公告)号：US20120126937A1
公开(公告)日：2012-05-24
申请号：US13296242
申请日：2011-11-15
申请人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
IPC分类号： G08B29/00
CPC分类号： G08B13/14 , G06Q10/087
摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.
摘要翻译：用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。键码单元位于受保护的环境中，与资产管理区域有关。设备单元可以存储设备标识码。键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备如果设备移动到资产管理区域外，则单元从密钥单元接收。

90. 发明申请

US20120083092A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120083092A1
公开(公告)日：2012-04-05
申请号：US13323033
申请日：2011-12-12
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

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