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81. 发明申请

US20090185742A1 METHOD FOR IMAGE COMPENSATION 审中-公开
标题翻译：图像补偿方法
公开(公告)号：US20090185742A1
公开(公告)日：2009-07-23
申请号：US12015908
申请日：2008-01-17
申请人： Shih-Chieh Lu , Ching-Hsiang Hsu , Ling-Chih Lu
发明人： Shih-Chieh Lu , Ching-Hsiang Hsu , Ling-Chih Lu
IPC分类号： G06K9/40 , G06K9/36
CPC分类号： H04N9/646 , G06T5/003 , G06T5/50 , G06T2207/20012 , G06T2207/20192 , G06T2207/20201 , H04N1/58
摘要： In an image compensation method, formats of images are identified based on ambient color quantity information. If the image is in text format or of high contrast, over compensation is barred to avoid edge effect. A compensation coefficient is set basing on edge eigenvalue of images. The compensation value is fine tuned based on a threshold value to obtain finer compensation result.
摘要翻译：在图像补偿方法中，基于环境颜色数量信息来识别图像的格式。如果图像为文本格式或高对比度，则过度补偿被禁止以避免边缘效应。基于图像的边缘特征值设置补偿系数。基于阈值对补偿值进行微调，以获得更精细的补偿结果。

82. 发明申请

US20070247902A1 METHOD FOR OPERATING A SINGLE-POLY SINGLE-TRANSISTOR NON-VOLATILE MEMORY CELL 有权
标题翻译：单晶单晶非易失性存储单元的操作方法
公开(公告)号：US20070247902A1
公开(公告)日：2007-10-25
申请号：US11625829
申请日：2007-01-23
申请人： Hsin-Ming Chen , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Hsin-Ming Chen , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C16/04
CPC分类号： G11C17/16 , G11C2216/26
摘要： A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.
摘要翻译：一种用于操作单晶体，单晶体管（1-T）非易失性存储器（NVM）单元的方法。 NVM单元包括在P基板上的栅极，栅极电介质层，N漏极区域和N源极区域。 N沟道定义在N漏极区域和N源极区域之间。 NVM单元通过分解栅极电介质层进行编程。为了读取NVM单元，向N漏极区域提供正电压，向栅极提供正电压，并将N源极区域和P基板接地。

83. 发明申请

US20070108507A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20070108507A1
公开(公告)日：2007-05-17
申请号：US11557974
申请日：2006-11-09
申请人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Shih-Chen Wang , Hsin-Ming Chen , Chun-Hung Lu , Ming-Chou Ho , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L29/788
CPC分类号： G11C16/0475 , G11C16/0425 , G11C16/0466 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/513 , H01L29/6656 , H01L29/66659 , H01L29/66825 , H01L29/66833 , H01L29/7835 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.
摘要翻译：提供了形成在第一导电型基板上的非易失性存储器。非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。栅极形成在第一导电类型的基板上。第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。第二面与第一面相反。

84. 发明申请

US20060017742A1 Method of one point color tracking 审中-公开
标题翻译：一点颜色跟踪方法
公开(公告)号：US20060017742A1
公开(公告)日：2006-01-26
申请号：US10896974
申请日：2004-07-23
申请人： Ching-Hsiang Hsu
发明人： Ching-Hsiang Hsu
IPC分类号： G09G5/02
CPC分类号： G09G5/06 , G06F3/04845 , G09G3/2003 , G09G3/3607 , G09G2320/0606 , G09G2320/0666 , G09G2320/0693 , G09G2360/14
摘要： A method of one point color tracking is for the color tracking of the screen panel that executes the tracking operation of the chromatic coordinates for the measured values of screen color parameter by using of the specific parameter values of the chromatic coordinates to get the screen color parameter tracking value and the lookup table of the color parameter tracking value, and to compare the color of the screen color parameter tracking value with the color of the measured values of screen color parameter so as to decide whether the steps of the color tracking stated above are repeated or not. Thereby, a method of one point color tracking can be provided for color display with high preciseness and steadiness. The method can suit for the color display devices such as liquid crystal display panels, plasma display panels, thin film transistor displays or organic light-emitting displays etc.
摘要翻译：一点颜色跟踪的方法是用于通过使用彩色坐标的特定参数值来执行屏幕颜色参数的测量值的色坐标的跟踪操作的屏幕面板的颜色跟踪，以获得屏幕颜色参数跟踪值和颜色参数跟踪值的查找表，并将屏幕颜色参数跟踪值的颜色与屏幕颜色参数的测量值的颜色进行比较，以便确定上述颜色跟踪的步骤是否为反复或不重复因此，可以以高精度和稳定的颜色显示提供一点颜色跟踪的方法。该方法适用于液晶显示面板，等离子体显示面板，薄膜晶体管显示器或有机发光显示器等彩色显示装置。

85. 发明申请

US20050214271A1 LACTOBACILLUS PARACASEI STRAIN GM-080 FOR TREATING ALLERGY RELATED DISEASES 有权
标题翻译： LACTOBACILLUS PARACASEI菌株GM-080用于治疗过敏相关疾病
公开(公告)号：US20050214271A1
公开(公告)日：2005-09-29
申请号：US10808503
申请日：2004-03-25
申请人： Ching-Hsiang Hsu , Wei-Chih Su , Ying-Yu Wang , Tzu-Chi Chang , Cheng-Wei Lai
发明人： Ching-Hsiang Hsu , Wei-Chih Su , Ying-Yu Wang , Tzu-Chi Chang , Cheng-Wei Lai
IPC分类号： A61K45/00 , C12N1/20 , C12R1/225
CPC分类号： C12R1/225 , C12N1/20 , Y10S435/853
摘要： The present invention provides an isolated microorganism strain, Lactobacillus paracasei GM-080, which is found to be effective in treating allergy. The use of the Lactobacillus paracasei GM-080 in treating allergy related disease is also provided.
摘要翻译：本发明提供了分离的微生物菌株，干酪乳酸杆菌GM-080，其被发现在治疗过敏中是有效的。也提供了副干酪乳酸杆菌GM-080在治疗过敏相关疾病中的应用。

86. 发明授权

US06914825B2 Semiconductor memory device having improved data retention 有权
标题翻译：具有改进的数据保持的半导体存储器件
公开(公告)号：US06914825B2
公开(公告)日：2005-07-05
申请号：US10249366
申请日：2003-04-03
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Ming-Chou Ho
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Ming-Chou Ho
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A NVM device encompasses a MOS select transistor including a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region. A MOS floating gate transistor is serially electrically connected to the MOS select transistor. The MOS floating gate transistor comprises a floating gate, a second source doping region electrically connected to the first drain doping region of the MOS select transistor, and a second drain doping region electrically connected to a bit line. The second source doping region and the second drain doping region define a floating gate channel. When the MOS floating gate transistor is programmed via a hot electron injection (HEI) mode, the floating gate is a P+ doped floating gate; when the MOS floating gate transistor is programmed via a hot hole injection (HHI) mode, the floating gate is an N+ doped floating gate.
摘要翻译： NVM器件包括MOS选择晶体管，其包括电连接到字线的选择栅极，电连接到源极线的第一源极掺杂区域和第一漏极掺杂区域。 MOS浮栅晶体管与MOS选择晶体管串联电连接。 MOS浮栅晶体管包括浮置栅极，电连接到MOS选择晶体管的第一漏极掺杂区域的第二源极掺杂区域和电连接到位线的第二漏极掺杂区域。第二源极掺杂区域和第二漏极掺杂区域限定浮动栅极沟道。当通过热电子注入（HEI）模式对MOS浮栅晶体管进行编程时，浮栅是P + 当通过热空穴注入（HHI）模式来编程MOS浮栅晶体管时，浮置栅极是掺杂N +的浮栅。

87. 发明申请

US20050098817A1 NON-VOLATILE MEMORY CELL 有权
标题翻译：非挥发性记忆细胞
公开(公告)号：US20050098817A1
公开(公告)日：2005-05-12
申请号：US10707700
申请日：2004-01-05
申请人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
发明人： Ching-Hsiang Hsu , Shih-Jye Shen , Hsin-Ming Chen , Hai-Ming Lee
IPC分类号： G11C16/04 , G11C16/10 , H01L21/8246 , H01L27/115 , H01L29/76 , H01L29/792 , H01L29/24
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/10 , H01L27/115 , H01L29/7923
摘要： A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.
摘要翻译：存储单元包括N型阱，三个P型掺杂区，第一层叠电介质层，第一栅极，第二堆叠电介质层和第二栅极。在N阱上形成三个P型掺杂区域。在三个P型掺杂区域中，第一电介质叠层形成在N型阱上，并且在第一掺杂区和第二掺杂区之间。第一栅极形成在第一堆叠电介质层上。在三个P型掺杂区域中，第二层叠电介质层形成在N型阱上，并且在第二掺杂区域和第三掺杂区域之间。第二栅极形成在第二堆叠电介质层上。

88. 发明授权

US06842374B2 Method for operating N-channel electrically erasable programmable logic device 有权
标题翻译：用于操作N沟道电可擦除可编程逻辑器件的方法
公开(公告)号：US06842374B2
公开(公告)日：2005-01-11
申请号：US10248283
申请日：2003-01-06
申请人： Kung-Hong Lee , Ching-Hsiang Hsu , Ya-Chin King , Shih-Jye Shen , Ming-Chou Ho
发明人： Kung-Hong Lee , Ching-Hsiang Hsu , Ya-Chin King , Shih-Jye Shen , Ming-Chou Ho
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11558 , H01L29/7885
摘要： An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate. By Applying a sufficient voltage on the first N-type doped region (VBL), and changing a select gate voltage (VSG) or the third N-type doped region voltage (VSL) applied on the second gate of the EEPLD, the operation of the EEPLD can be selectively implemented either under a channel hot hole (CHH) program mode or a channel hot electron (CHE) erase mode.
摘要翻译：电可擦除可编程逻辑器件（EEPLD）包含P型衬底。第一N型掺杂区域设置在P型衬底中。用于存储数据的第一栅极覆盖P型衬底并与第一N型掺杂区域相邻。第二N型掺杂区域横向设置在P型衬底中。第二N型掺杂区域也与第一栅极相邻。作为EEPLD的选择栅极或选择栅极的第二栅极覆盖P型衬底并与第二N型掺杂区域相邻。在P型衬底中设置第三N型掺杂区域。第三N型掺杂区域与第二栅极相邻。通过在第一N型掺杂区域（VBL）上施加足够的电压，并且改变施加在EEPLD的第二栅极上的选择栅极电压（VSG）或第三N型掺杂区域电压（VSL），操作可以在通道热孔（CHH）编程模式或通道热电子（CHE）擦除模式）下选择性地实施EEPLD。

89. 发明授权

US06770950B2 Non-volatile semiconductor memory structure 失效
标题翻译：非易失性半导体存储器结构
公开(公告)号：US06770950B2
公开(公告)日：2004-08-03
申请号：US10099801
申请日：2002-03-13
申请人： Ching-Song Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Song Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L2900
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/7885 , H01L29/792 , Y10S257/928
摘要： A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.
摘要翻译：非挥发性半导体存储单元结构及其制造方法。该方法包括以下步骤：在衬底上形成浅的第一类型阱层，第二类型阱层和深度第一类型阱层，在浅的第一类型阱层上形成堆叠栅极，最后形成源极端子; 漏极端子。源极穿透浅的第一类型阱层并与第二类型阱层连接。漏极端子靠近浅第一型阱层的表面。源极端子和漏极端子都包含第二种掺杂剂。

90. 发明授权

US06757940B2 Hinge for a notebook computer 失效
标题翻译：铰链用于笔记本电脑
公开(公告)号：US06757940B2
公开(公告)日：2004-07-06
申请号：US10298093
申请日：2002-11-18
申请人： Sheng-Nan Lu , Ching-Hsiang Hsu
发明人： Sheng-Nan Lu , Ching-Hsiang Hsu
IPC分类号： E05D1110
CPC分类号： G06F1/1681 , E05D11/1078 , E05Y2900/606 , G06F1/1616 , Y10T16/5387 , Y10T16/540255 , Y10T16/540345
摘要： A hinge for a notebook computer is composed of a first seat, a second seat and an axle. The first seat is mounted on a monitor, and the second seat is mounted on a body. The axle is securely mounted on the first seat and pivotally mounted on the second seat. Two sleeves are provided outside the axle and engaged with each other in a closed status. The first sleeve has two lugs received in a channel defined in the second sleeve. The second sleeve has two protrusive portions respectively formed at two sides of the channel, and two cambered surfaces formed between the channel and the protrusive portion. When a user lowers the monitor to a position that the lugs enter into the cambered surfaces, the monitor can automatically descend under the effect of gravity and the force of a resilient member.
摘要翻译：用于笔记本电脑的铰链由第一座椅，第二座椅和车轴组成。第一座位安装在监视器上，第二座椅安装在主体上。车轴牢固地安装在第一座椅上并可枢转地安装在第二座椅上。在轴外设置两个袖子，并处于关闭状态。第一套筒具有接收在限定在第二套筒中的通道中的两个凸耳。第二套筒具有分别形成在通道的两侧的两个突出部分，以及形成在通道和突出部分之间的两个弧形表面。当用户将显示器降低到凸耳进入弧形表面的位置时，显示器可以在重力和弹性构件的力的作用下自动下降。

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