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81. 发明授权

US07305593B2 Memory mapping for parallel turbo decoding 失效
标题翻译：并行turbo解码的内存映射
公开(公告)号：US07305593B2
公开(公告)日：2007-12-04
申请号：US10648038
申请日：2003-08-26
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由多路复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

82. 发明授权

US07065606B2 Controller architecture for memory mapping 失效
标题翻译：用于内存映射的控制器架构
公开(公告)号：US07065606B2
公开(公告)日：2006-06-20
申请号：US10655191
申请日：2003-09-04
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
IPC分类号： G06F12/00
CPC分类号： G06F12/04
摘要： The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories. The apparatus may include: (a) a plurality of physical memories onto which a customer memory may be mapped, each of physical memories having a data width of m blocks, the customer memory having a data width of k blocks, and k and m being integers; (b) an address controller, communicatively coupled to a plurality of physical memories, for receiving first address information of the customer memory, for outputting second address information to a plurality of physical memories, and for outputting index information; (c) a data input controller, communicatively coupled to the address controller and a plurality of physical memories, for receiving data of the customer memory and the index information, and for outputting data with a data width of m blocks to a plurality of physical memories; and (d) a data output controller, communicatively coupled to a plurality of physical memories and to the address controller though a delay unit, for receiving the index information, for receiving output, with a width of said m blocks, of a plurality of physical memories, and for outputting the customer memory with a width of said k blocks.
摘要翻译：本发明涉及一种用于将顾客存储器映射到多个物理存储器上的方法和装置。该装置可以包括：（a）可以映射客户存储器的多个物理存储器，每个物理存储器具有m个块的数据宽度，该客户存储器的数据宽度为k个块，k和m为整数（b）地址控制器，通信地耦合到多个物理存储器，用于接收客户存储器的第一地址信息，用于将第二地址信息输出到多个物理存储器，并用于输出索引信息; （c）数据输入控制器，通信地耦合到地址控制器和多个物理存储器，用于接收客户存储器的数据和索引信息，并且用于将数据宽度为m个块的数据输出到多个物理存储器 ; 以及（d）数据输出控制器，通信地耦合到多个物理存储器，并通过延迟单元与地址控制器通信，用于接收索引信息，用于接收具有所述m个块的宽度的多个物理存储器，并输出具有所述k个块的宽度的客户存储器。

83. 发明授权

US06886088B2 Memory that allows simultaneous read requests 失效
标题翻译：允许同时读取请求的内存
公开(公告)号：US06886088B2
公开(公告)日：2005-04-26
申请号：US10308334
申请日：2002-12-03
申请人： Egor A. Andreev , Anatoli A. Bolotov , Ranko Scepanovic , Alexander E. Andreev
发明人： Egor A. Andreev , Anatoli A. Bolotov , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F12/00 , G06F13/00 , G11C5/00
CPC分类号： G11C5/00 , G11C5/04 , G11C7/22 , G11C2207/2209
摘要： The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary memory sub-modules and an additional memory sub-module including a sum of values located in the at least two primary memory sub-modules at corresponding addresses. The sum of the additional memory module enables at least two simultaneous read requests to be performed.
摘要翻译：本发明涉及允许具有改进的密度的两个同时读取请求的存储器。在本发明的一个方面，存储器模块包括至少两个主存储器子模块和附加的存储器子模块，该附加存储器子模块包括位于相应地址处的至少两个主存储器子模块中的值之和。附加存储器模块的总和使得能够执行至少两个同时的读取请求。

84. 发明授权

US06842750B2 Symbolic simulation driven netlist simplification 失效
标题翻译：符号模拟驱动网表简化
公开(公告)号：US06842750B2
公开(公告)日：2005-01-11
申请号：US10108286
申请日：2002-03-27
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F7/00 , G06F17/30 , G06F17/50
CPC分类号： G06F17/5022 , Y10S707/99931 , Y10S707/99933 , Y10S707/99935 , Y10S707/99936 , Y10S707/99943
摘要： The present invention is directed to a simplification method for an arbitrary library. In aspects of the present invention, the method does not rely on specific properties of the library elements and has linear complexity. The present invention may be implemented based on a symbolic simulation in an alphabet which contains 0, 1, symbols of variables, and negations of the variables' symbols. In an aspect of the present invention, a method for reducing redundancy in a simulation through use of a symbolic simulation utilizing an arbitrary library includes receiving a set A of values, the set A including input variables which are elements of the set A. Symbols of the input variables are constructed in which like and similar variables share a like symbol and a similar symbol respectively. A table of output values computed from a table of a Boolean operator employing the constructed symbols of the input variable is formed, the constructed symbols formed to reduce redundancy.
摘要翻译：本发明涉及一种用于任意库的简化方法。在本发明的方面中，该方法不依赖于库元件的特定属性并且具有线性复杂性。本发明可以基于包含0,1，变量符号和变量符号的否定的字母表中的符号模拟来实现。在本发明的一个方面中，通过使用利用任意库的符号仿真减少仿真中的冗余度的方法包括：接收一组值A，该集合A包括作为集合A的元素的输入变量。构造输入变量，其中类似和类似的变量分别共享相似的符号和相似的符号。形成从使用输入变量的构造符号的布尔运算符的表计算出的输出值的表，形成了构造的符号以减少冗余。

85. 发明授权

US06804811B2 Process for layout of memory matrices in integrated circuits 有权
标题翻译：集成电路中存储矩阵布局的过程
公开(公告)号：US06804811B2
公开(公告)日：2004-10-12
申请号：US10254616
申请日：2002-09-25
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G11C5/063
摘要： A memory module is formed on an integrated circuit by arranging memory cells in columns, and routing signal wires from module pins at an edge of the module to respective memory cells. The module pins are optimally positioned relative to the memory cells, and routing wires extend from the pins along routing lines to the cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.
摘要翻译：存储器模块通过将存储器单元布置在列中而形成在集成电路上，并且将信号线从模块的边缘处的模块引脚路由到相应的存储器单元。模块引脚相对于存储单元最佳定位，并且布线从引脚沿着布线线延伸到单元。缓冲通道被定义在存储器单元之间并与列垂直的位置上，并且通过在每个缓冲通道中放置多个缓冲器将缓冲器选择性地插入到缓冲通道中的路由布线中。识别要在缓冲通道缓冲的信号线，并且信号线被路由到每个缓冲通道，使得（i）要缓冲的信号线被重新路由到缓冲器的输入和输出，以及（ii）所有其他信号线沿其各自的路由线路由。

86. 发明授权

US06795954B2 Method of decreasing instantaneous current without affecting timing 失效
标题翻译：降低瞬时电流而不影响定时的方法
公开(公告)号：US06795954B2
公开(公告)日：2004-09-21
申请号：US10278150
申请日：2002-10-21
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： B06F1750
CPC分类号： G06F17/5045
摘要： A method of calculating skews for memory cells and flip-flops in a circuit design to reduce peak power includes receiving a circuit design containing memory cells and other clocked cells; constructing a first graph that includes a union of all inputs, vertices representative of the memory cells and the other clocked cells, a union of all outputs, and edges between the vertices each having a length equal to a delay between corresponding vertices minus a clock period; constructing a second graph having vertices representative of only the memory cells and corresponding edges such that the maximum length between any two corresponding vertices is less than zero; calculating a skew for each of the memory cells from the second graph; constructing a third graph from the first graph by merging the vertices of the memory cells into a single vertex; calculating a skew for each of the other clocked cells from the third graph; normalizing each skew calculated for the other clocked cells; recalculating the skew for each of the memory cells from the normalized skew calculated for the other clocked cells; and generating as output the recalculated skew for each of the memory cells.
摘要翻译：在电路设计中计算存储单元和触发器的斜率以减少峰值功率的方法包括接收包含存储器单元和其它定时单元的电路设计; 构建包括所有输入的并集，表示存储器单元的顶点和其它时钟单元的第一图形，所有输出的并集以及顶点之间的边缘，每个顶点之间的长度等于相应顶点之间的延迟减去时钟周期 ; 构造具有仅代表存储器单元和对应边缘的顶点的第二图形，使得任何两个对应顶点之间的最大长度小于零; 从所述第二图计算每个所述存储器单元的偏差; 通过将存储器单元的顶点合并为单个顶点从第一图形构造第三图; 从第三个图形计算每个其他计时单元的偏差; 归一化为其他计时单元计算的每个偏移量; 从为其他计时单元计算的归一化偏差重新计算每个存储器单元的偏移; 并产生每个存储器单元的重新计算的偏移量作为输出。

87. 发明授权

US06735600B1 Editing protocol for flexible search engines 失效
标题翻译：灵活搜索引擎的编辑协议
公开(公告)号：US06735600B1
公开(公告)日：2004-05-11
申请号：US09822969
申请日：2001-03-30
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1700
CPC分类号： G06F17/30961 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945 , Y10S707/99948
摘要： Entries are added or deleted on a search tree starting with a selected vertex on an identified level of the tree. If the level of the selected vertex is the bottom level the entry is inserted to or deleted from the selected vertex. If the level of the selected vertex is not the bottom level, the entries on the child vertices of the selected vertex are redistributed so that the child vertex having a maximal index contains a predetermined number of entries. If the level of the child vertex is the bottom level the entry is inserted to or deleted from the child vertex. Otherwise, the process repeats, using the child and grandchild vertices, until the correct level is reached.
摘要翻译：在搜索树上添加或删除条目，从树的标识级别上的选定顶点开始。如果所选顶点的级别是底层，则条目将被插入到所选顶点或从所选顶点中删除。如果所选顶点的级别不是底层，则所选顶点的子顶点上的条目被重新分配，使得具有最大索引的子顶点包含预定数量的条目。如果子顶点的级别是底层，则条目将插入到子顶点或从子顶点删除。否则，该过程将重复，使用子孙和顶点，直到达到正确的级别。

88. 发明授权

US06564211B1 Fast flexible search engine for longest prefix match 有权
标题翻译：快速灵活的搜索引擎，用于最长的前缀匹配
公开(公告)号：US06564211B1
公开(公告)日：2003-05-13
申请号：US09679209
申请日：2000-10-04
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , Y10S707/99933 , Y10S707/99936
摘要： A subprefix is selected from a prefix search tree that has a longest match to a search prefix. A binary search prefix is input to the root vertex of the tree, and is compared to the prefixes in selected hierarchy vertices. A bit is set in a search mask based on a least significant bit of a bit string in the search prefix that matches a longest bit string in a prefix in each vertex. A longest matching subprefix is selected from a string of most significant bits of the search prefix based on the lowest significant bit set in the search mask. A prefix mask is also provided for each prefix in the tree, and is useful in connection with construction of the search mask.
摘要翻译：从与搜索前缀最长匹配的前缀搜索树中选择子扩展名。将二叉搜索前缀输入到树的根顶点，并将其与所选层次顶点中的前缀进行比较。基于搜索前缀中与每个顶点中的前缀中最长位串匹配的位串的最低有效位，将一位设置在搜索掩码中。基于搜索掩码中设置的最低有效位，从搜索前缀的最高有效位的串中选择最长的匹配子预混。还为树中的每个前缀提供前缀掩码，并且与搜索掩码的构造有关。

89. 发明授权

US06526553B1 Chip core size estimation 有权
标题翻译：芯片尺寸估算
公开(公告)号：US06526553B1
公开(公告)日：2003-02-25
申请号：US09837492
申请日：2001-04-18
申请人： Alexander E. Andreev , Ranko Scepanovic , Ivan Pavisic
发明人： Alexander E. Andreev , Ranko Scepanovic , Ivan Pavisic
IPC分类号： G06E945
CPC分类号： G06F17/5072
摘要： A minimum core size of an integrated circuit chip is estimated for given parameters of an existing technology. The average wire length for the nets is calculated, and the centers of each cell are assigned to x,y coordinates to minimize wire length. The widths of routing channels between consecutive columns, and their associated core sizes are estimated based on the cell placement and the existing technology parameters. The minimum core size is identified from the estimated core sizes.
摘要翻译：对现有技术的给定参数估计集成电路芯片的最小核心尺寸。计算网络的平均线长度，并将每个单元格的中心分配给x，y坐标以最小化线长度。基于单元格放置和现有技术参数，估计连续列之间的路由通道的宽度及其相关的核心大小。从估计的核心尺寸确定最小核心尺寸。

90. 发明授权

US06312980B1 Programmable triangular shaped device having variable gain 失效
标题翻译：具有可变增益的可编程三角形器件
公开(公告)号：US06312980B1
公开(公告)日：2001-11-06
申请号：US09092827
申请日：1998-06-05
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L2182
CPC分类号： H01L27/108 , G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/528 , H01L27/11 , H01L27/1104 , H01L27/11807 , H01L29/0657 , H01L2924/0002 , Y10S438/965 , H01L2924/00
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

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