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1. 发明授权

US07050582B1 Pseudo-random one-to-one circuit synthesis 有权
标题翻译：伪随机一对一电路合成
公开(公告)号：US07050582B1
公开(公告)日：2006-05-23
申请号：US09883733
申请日：2001-06-18
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/0668
摘要： A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the input signal among a plurality of block input signals, (B) establishing a plurality of transfer functions where each transfer function may be configured to present a plurality of unique symbols as a block output signal responsive to said block input signal, and (C) concatenating the block output signals to form the output signal.
摘要翻译：一种定义输入信号和输出信号之间变换的方法。该转换可以实现可以在硬件和/或软件中实现或以软件建模的伪随机一对一功能。该方法可以包括以下步骤：（A）在多个块输入信号之间分配输入信号，（B）建立多个传递函数，其中每个传递函数可被配置为呈现多个唯一符号作为块输出信号响应于所述块输入信号，以及（C）串联块输出信号以形成输出信号。

2. 发明授权

US07065606B2 Controller architecture for memory mapping 失效
标题翻译：用于内存映射的控制器架构
公开(公告)号：US07065606B2
公开(公告)日：2006-06-20
申请号：US10655191
申请日：2003-09-04
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
IPC分类号： G06F12/00
CPC分类号： G06F12/04
摘要： The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories. The apparatus may include: (a) a plurality of physical memories onto which a customer memory may be mapped, each of physical memories having a data width of m blocks, the customer memory having a data width of k blocks, and k and m being integers; (b) an address controller, communicatively coupled to a plurality of physical memories, for receiving first address information of the customer memory, for outputting second address information to a plurality of physical memories, and for outputting index information; (c) a data input controller, communicatively coupled to the address controller and a plurality of physical memories, for receiving data of the customer memory and the index information, and for outputting data with a data width of m blocks to a plurality of physical memories; and (d) a data output controller, communicatively coupled to a plurality of physical memories and to the address controller though a delay unit, for receiving the index information, for receiving output, with a width of said m blocks, of a plurality of physical memories, and for outputting the customer memory with a width of said k blocks.
摘要翻译：本发明涉及一种用于将顾客存储器映射到多个物理存储器上的方法和装置。该装置可以包括：（a）可以映射客户存储器的多个物理存储器，每个物理存储器具有m个块的数据宽度，该客户存储器的数据宽度为k个块，k和m为整数（b）地址控制器，通信地耦合到多个物理存储器，用于接收客户存储器的第一地址信息，用于将第二地址信息输出到多个物理存储器，并用于输出索引信息; （c）数据输入控制器，通信地耦合到地址控制器和多个物理存储器，用于接收客户存储器的数据和索引信息，并且用于将数据宽度为m个块的数据输出到多个物理存储器 ; 以及（d）数据输出控制器，通信地耦合到多个物理存储器，并通过延迟单元与地址控制器通信，用于接收索引信息，用于接收具有所述m个块的宽度的多个物理存储器，并输出具有所述k个块的宽度的客户存储器。

3. 发明授权

US08566769B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08566769B2
公开(公告)日：2013-10-22
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

4. 发明申请

US20100023904A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20100023904A1
公开(公告)日：2010-01-28
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

5. 发明授权

US08245168B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US08245168B2
公开(公告)日：2012-08-14
申请号：US12508320
申请日：2009-07-23
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

6. 发明申请

US20120278775A1 Method and Apparatus for Generating Memory Models and Timing Database 失效
标题翻译：用于生成内存模型和时序数据库的方法和装置
公开(公告)号：US20120278775A1
公开(公告)日：2012-11-01
申请号：US13547884
申请日：2012-07-12
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

7. 发明授权

US07584442B2 Method and apparatus for generating memory models and timing database 失效
标题翻译：用于生成内存模型和计时数据库的方法和装置
公开(公告)号：US07584442B2
公开(公告)日：2009-09-01
申请号：US11298894
申请日：2005-12-09
申请人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
发明人： Alexandre Andreev , Andrey Nikitin , Ranko Scepanovic , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.
摘要翻译：提供了一种用于创建和使用存储器定时数据库的方法和装置。定义了多个表征存储器，其可被映射到存储器资源。每个表征存储器具有不同的存储器参数。还定义了将每个表征存储器平铺到存储器资源的多种变型。每个表征存储器的每个平铺变体的时序特征基于输入夯实值和输出负载的集合存储在用于存储器资源的存储器定时数据库中。

8. 发明授权

US07822099B2 Digital Gaussian noise simulator 有权
标题翻译：数字高斯噪声模拟器
公开(公告)号：US07822099B2
公开(公告)日：2010-10-26
申请号：US11758975
申请日：2007-06-06
申请人： Andrey A. Nikitin , Alexander E. Andreev , Igor A. Vikhliantsev
发明人： Andrey A. Nikitin , Alexander E. Andreev , Igor A. Vikhliantsev
IPC分类号： H04B1/69 , G06F1/02 , G06F7/58 , H03K3/84
CPC分类号： G06F17/18
摘要： A Gaussian noise is simulated by discrete analogue ri,j. A first parameter α and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on α, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of α = 2 B - A 2 B and D>i≧0 and 2C>j≧0, where B≧0, 2B>A>0, C≧1 and D≧1, and magnitude s i , j = 1 - α i + α i · 1 - α 2 C · j ⁢ ⁢ or ⁢ ⁢ s D - 1 , j = 1 - α D - 1 + α D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on α and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.
摘要翻译：高斯噪声由离散模拟ri，j模拟。选择第一参数α和多个第一和第二整数i和j。识别多个点i，j，并且基于α，i和j针对每个点计算幅度si，j。离散的模拟ri，j基于相应的si，j。给出α= 2 B-A 2 B和D> i≥0和2C>j≥0的实例，其中B≥0,2B> A> 0，C≥1和D≥1，并且幅度si，j = 1-αi +αi·1-α2 C·j·肯·杜·斯D-1，j = 1-αD-1 +αD·1·1 2 C·j。在一些实施例中，基于α和i定义段。根据j的相应值将该段划分成点，并且对该段的每个点计算大小。对于i的每个值迭代地重复定义和分割段并计算幅度。

9. 发明授权

US07210113B2 Process and apparatus for placing cells in an IC floorplan 有权
标题翻译：将电池放置在IC平面图中的工艺和设备
公开(公告)号：US07210113B2
公开(公告)日：2007-04-24
申请号：US10830542
申请日：2004-04-23
申请人： Alexander E. Andreev , Andrey A. Nikitin , Igor A. Vikhliantsev
发明人： Alexander E. Andreev , Andrey A. Nikitin , Igor A. Vikhliantsev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. The coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.
摘要翻译：通过在模块中创建单元格群，将单元格放置在集成电路平面布置图中，每个簇由连接到模块中的至少一个触发器的路径中的单元或者不连接到任何翻转的路径的单元组成 -flop。区域在布局图中定义，用于放置模块，并将集群放置在模块中的最佳位置，并将模块放置在区域中的最佳位置。有选择地重新计算电线，模块和集群的坐标。群集在平面图中移动以获得更均匀的密度，并且将模块分配给基于模块坐标的区域。

10. 发明授权

US06941533B2 Clock tree synthesis with skew for memory devices 失效
标题翻译：用于存储器件的时钟树合成与偏斜
公开(公告)号：US06941533B2
公开(公告)日：2005-09-06
申请号：US10277398
申请日：2002-10-21
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ivan Pavisic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ivan Pavisic
IPC分类号： G06F1/10 , G06F17/50
CPC分类号： G06F17/5077 , G06F1/10 , G06F17/5045 , G06F2217/62
摘要： A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.
摘要翻译：一种合成用于降低集成电路设计中的峰值功率的时钟树的方法包括将电路设计划分成一组存储器单元和一组非存储器单元，将该组存储器单元分成段，构建第一时钟树具有对于每个段具有对应的初始偏移的第一根顶点，构造具有第二根顶点的第二时钟树，该第二根顶点具有用于所述非存储器单元组的对应的初始偏移，延迟平衡所述第一根顶点和所述第二顶点时钟树，并且在第一根顶点和第二根顶点之间的中点处插入时钟缓冲器。

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