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81. 发明授权

US5406131A Exponential circuit 失效
标题翻译：指数电路
公开(公告)号：US5406131A
公开(公告)日：1995-04-11
申请号：US174064
申请日：1993-12-28
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/16 , G04F10/10 , G06G7/20 , H03K4/00 , H03K19/00
CPC分类号： G04F10/10
摘要： An exponential circuit according to the present invention converts voltage level to time by using a charged voltage of RC circuit RC.sub.1, registers time as a clock number at a digital counter and performs bit shift for the registered data.
摘要翻译：根据本发明的指数电路通过使用RC电路RC1的充电电压将电压电平转换为时间，在数字计数器处将时间作为时钟数进行登记，并对登记的数据执行位移。

82. 发明授权

US5319317A Voltage follower circuit 失效
标题翻译：电压跟随电路
公开(公告)号：US5319317A
公开(公告)日：1994-06-07
申请号：US986809
申请日：1992-12-08
申请人： Guoliang Shou , Weikang Yang , Wiwat Wongwarawipat , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Wiwat Wongwarawipat , Sunao Takatori , Makoto Yamamoto
IPC分类号： H03F3/50 , H03K19/017 , H03F3/26
CPC分类号： H03K19/01721 , H03F3/505
摘要： A voltage follower circuit comprising an nMOS transistor whose drain is connected to a power source and a pMOS transistor whose drain is connected to the source of the nMOS transistor and whose source is grounded, wherein input voltage is connected to the gates of nMOS and pMOS transistor. A source of the nMOS transistor is connected to an output terminal, and the output terminal is grounded through capacitance.
摘要翻译：一种电压跟随器电路，其包括漏极连接到电源的nMOS晶体管和漏极连接到nMOS晶体管的源极并且其源极接地的pMOS晶体管，其中输入电压连接到nMOS和pMOS晶体管的栅极。 nMOS晶体管的源极连接到输出端子，并且输出端子通过电容接地。

83. 发明授权

US06370130B1 Spread spectrum communication system 失效
标题翻译：扩频通信系统
公开(公告)号：US06370130B1
公开(公告)日：2002-04-09
申请号：US09092914
申请日：1998-06-08
申请人： Changming Zhou , Guoliang Shou , Xuping Zhou , Kunihiko Suzuki , Makoto Yamamoto
发明人： Changming Zhou , Guoliang Shou , Xuping Zhou , Kunihiko Suzuki , Makoto Yamamoto
IPC分类号： H04B7216
CPC分类号： H04B1/7077 , H04B1/70735 , H04B1/708 , H04B7/2628 , H04B2201/70702 , H04B2201/7071
摘要： A receiver for spread spectrum communication system receives a traffic channel and common control channel by a plurality of matched filters at least one of which is selectively available for the traffic or the common control channel. At the initial acquisition, a plurality of matched filters are used for receiving the common control channel. At the hand-over, a plurality of matched filters are used to receive traffic channels of the current base station and the base stations in the adjacent cells.
摘要翻译：用于扩频通信系统的接收机通过多个匹配滤波器接收业务信道和公共控制信道，其中至少一个匹配滤波器可选择地可用于业务或公共控制信道。在初始采集时，使用多个匹配滤波器来接收公共控制信道。在切换时，使用多个匹配滤波器来接收当前基站和相邻小区中的基站的业务信道。

84. 发明授权

US06278724B1 Receiver in a spread spectrum communication system having low power analog multipliers and adders 失效
标题翻译：具有低功耗模拟乘法器和加法器的扩频通信系统中的接收机
公开(公告)号：US06278724B1
公开(公告)日：2001-08-21
申请号：US09032776
申请日：1998-03-06
申请人： Changming Zhou , Guoliang Shou , Kunihiko Suzuki , Xuping Zhou , Xiaoling Qin , Jie Chen , Mamoru Sawahashi , Fumiyuki Adachi
发明人： Changming Zhou , Guoliang Shou , Kunihiko Suzuki , Xuping Zhou , Xiaoling Qin , Jie Chen , Mamoru Sawahashi , Fumiyuki Adachi
IPC分类号： H04L2732
CPC分类号： H04B1/7113 , H04B1/7117 , H04B1/712 , H04B1/7183
摘要： A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks. A rake combiner synchronously combines the phase-corrected de-spread received signals of each path.
摘要翻译：扩频通信系统中的信号接收装置仅需要少量的电路并消耗少量的电力。正交检测器将接收信号分解为同相分量和正交分量，并将其提供给复合型匹配滤波器。复合型匹配滤波器对同相分量和正交分量进行解扩，并将它们发送到多路径选择器。多径选择器从接收到的解扩信号中选择具有高电平信号电功率的多个路径，并将所选择的路径的接收信号发送到多个相位校正块。模拟运算电路计算每个路径的两个连续导频符号块的接收信号的相位误差。模拟运算电路校正在两个连续的导频符号块之间已经接收到的信息符号块的接收信号的相位。瑞克组合器同步地组合每个路径的相位校正的去扩展接收信号。

85. 发明授权

US06252899B1 Complex despreading system 失效
标题翻译：复杂解扩系统
公开(公告)号：US06252899B1
公开(公告)日：2001-06-26
申请号：US09055346
申请日：1998-04-06
申请人： Chanming Zhou , Guoliang Shou
发明人： Chanming Zhou , Guoliang Shou
IPC分类号： H04L2730
CPC分类号： H04B1/7093
摘要： A compact and easily-assembled circuit for a complex despreading system, arranged such that the circuit does not contain pairs of adders at the output area. The configuration of the circuit enables the addition and subtraction of different signal components to occur before the multiplication stage and not at a pair of adders located at the output area The complex despreader system employs a complex matched filter at a receiver for despreading received signals with a QPSK system in the primary modulation and a BPSK system in the secondary modulation modulated at a transmitter. The input area of each matched filter of I and Q channels includes a pair of adders. One adder generates a first signal having a positive in-phase and a positive quadrature component. The other adder generates a second signal having a negative in-phase component and a positive quadrature component. Next, an I-channel multiplication circuit multiplies both components of the first signal by a spread code then adds the multiplication results together. Likewise, a Q-channel multiplication and addition circuit multiplies the components of the second signal by a spread code and then adds the multiplication results together.
摘要翻译：一种用于复杂解扩系统的紧凑且容易组装的电路，其布置成使得该电路在输出区域不包含加法器对。电路的配置使得不同信号分量的相加和减法在乘法阶段之前发生，而不是在位于输出区的一对加法器处。复数解扩器系统在接收机处采用复匹配滤波器来解扩接收信号一次调制中的QPSK系统和在发射机调制的二次调制中的BPSK系统。 I和Q通道的每个匹配滤波器的输入区域包括一对加法器。一个加法器产生具有正同相和正正交分量的第一信号。另一个加法器产生具有负同相分量和正正交分量的第二信号。接下来，I信道乘法电路将第一信号的两个分量乘以扩展码，然后将乘法结果相加。同样，Q信道乘法和加法电路将第二信号的分量乘以扩展码，然后将相乘结果相加。

86. 发明授权

US06212219B1 Spread spectrum communication system 失效
标题翻译：扩频通信系统
公开(公告)号：US06212219B1
公开(公告)日：2001-04-03
申请号：US08780137
申请日：1996-12-26
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04L2730
CPC分类号： H04J13/0022 , H04J13/10 , H04J2013/0037
摘要： The present invention has an object to provide a spread spectrum communication system for heightening the speed of communication. The present invention transfers the first PN code sequence itself as the first component, adds and transfers zero or more instances of the second PN code sequence given a phase difference as the second component, and defines an information for transmitting by the number of the second PN codes corresponding to a cycle of said first PN code sequence.
摘要翻译：本发明的目的是提供一种用于提高通信速度的扩频通信系统。本发明将第一PN码序列本身作为第一分量传送，将给定相位差的第二PN码序列的零个或多个实例相加并传送作为第二分量，并且定义用于通过第二PN 对应于所述第一PN码序列的周期的码。

87. 发明授权

US6025752A Inverting amplifying circuit 失效
标题翻译：反相放大电路
公开(公告)号：US6025752A
公开(公告)日：2000-02-15
申请号：US087924
申请日：1998-06-01
申请人： Changming Zhou , Guoliang Shou , Shengmin Lin , Takashi Tomatsu , Jie Chen
发明人： Changming Zhou , Guoliang Shou , Shengmin Lin , Takashi Tomatsu , Jie Chen
IPC分类号： H03F1/30 , H03F3/00 , H03F1/14
CPC分类号： H03F1/303 , H03F3/005
摘要： An inverting amplifying circuit for outputting an inversion of an input with good linearity, having an inverter circuit, a feedback capacitance, an input capacitance, a first refresh switch, a second refresh switch, a sleep switch, and a first cutoff switch. A sleep voltage is input through the sleep switch to the inverter circuit for minimizing the electrical power consumption. The sleep switch connects a terminal of the inverter circuit directly to ground when in a sleep mode. The first cut off switch is connected between an output of the inverter circuit and an output of the inverting amplifying circuit.
摘要翻译：一种用于输出具有良好线性度的输入的反相的反相放大电路，具有反相器电路，反馈电容，输入电容，第一刷新开关，第二刷新开关，休眠开关和第一截止开关。睡眠电压通过睡眠开关输入到逆变器电路，以最小化电力消耗。休眠开关在休眠模式下将逆变器电路的端子直接连接到地。第一截止开关连接在逆变器电路的输出端和反相放大电路的输出端之间。

88. 发明授权

US5973538A Sensor circuit 失效
标题翻译：传感器电路
公开(公告)号：US5973538A
公开(公告)日：1999-10-26
申请号：US882224
申请日：1997-06-25
申请人： Guoliang Shou , Kazunori Motohashi , Shengmin Lin , Makoto Yamamoto , Toshiyuki Matsumoto , Muneo Harada , Takahiko Ooasa , Yoshihiro Hirota
发明人： Guoliang Shou , Kazunori Motohashi , Shengmin Lin , Makoto Yamamoto , Toshiyuki Matsumoto , Muneo Harada , Takahiko Ooasa , Yoshihiro Hirota
IPC分类号： G01D5/24 , G01D5/16 , G01D5/241 , G06G7/42
CPC分类号： G01D5/24 , G01D5/16 , G01D5/2417
摘要： A small sensor circuit with reducible electric power consumption is formed by connecting inverting amplifiers comprised of CMOS inverters connected in an odd number of stages, in series to guarantee the linearity of the relationship between inputs and outputs, and connecting an impedance as a sensor between the inputs and outputs, or to an input.
摘要翻译：具有可降低功耗的小型传感器电路通过将由奇数级连接的CMOS反相器组成的反相放大器串联连接形成，以确保输入和输出之间的关系线性，并将阻抗作为传感器连接在输入和输出，或输入。

89. 发明授权

US5945875A .pi./n shift phase-shift keying demodulator 失效
标题翻译： pi / n移相移键控解调器
公开(公告)号：US5945875A
公开(公告)日：1999-08-31
申请号：US47457
申请日：1998-03-25
申请人： Xuping Zhou , Guoliang Shou , Changming Zhou
发明人： Xuping Zhou , Guoliang Shou , Changming Zhou
IPC分类号： H04L27/22 , H04L27/233 , H03D3/00
CPC分类号： H04L27/2331
摘要： A .pi./n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through .pi./4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by .pi./8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.
摘要翻译：本发明的π/ n移位PSK解调器通过以下方法由数字逻辑装置形成。 XOR4通过从SH2输出的pi / 4移位QPSK和SH1的前一个输出来计算当前采样之间的异或运算。在第一操作装置5中从XOR4的输出中累积1，并将其乘以pi / 8获得当前和先前符号之间的绝对相位差。来自SH1的前者或后者的四位从SH2的相应的前一个或后四位中减去，每个位的结果被相加，并且其符号被加到符号加法装置10中的绝对相位数据。在相位偏移为从10的输出中减去，在判断电路13中被解调成原来的。

90. 发明授权

US5862070A Discrete cosine transformation circuit 失效
标题翻译：离散余弦变换电路
公开(公告)号：US5862070A
公开(公告)日：1999-01-19
申请号：US820002
申请日：1997-03-18
申请人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
发明人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
IPC分类号： G06F17/14 , G06G7/22 , G06G7/02 , G06G7/19
CPC分类号： G06G7/22 , G06F17/147
摘要： A high-speed discrete cosine transformation circuit includes the one-dimensional input signals x(0) to x(7) being input in parallel to the positive input terminals "+" or the negative input terminals "-" of eight neural operation units (NOU) 11 to 18 through capacitors d0 to d6. In each NOU 11 to 18, input signals x(0) to x(7) are added and subtracted. Input signals x(0) to x(7) are multiplied beforehand by the coefficient in proportion to the capacities of capacitors d0 to d6 which are connected to NOU 11 to 18. Thereafter, discrete cosine transforming coefficients y(0) to y(7) are output. A two-dimensional discrete cosine transformation circuit is realized by using the one-dimensional discrete cosine transforming circuit.
摘要翻译：高速离散余弦变换电路包括与八个神经运算单元的正输入端子“+”或负输入端子“ - ”并联输入的一维输入信号x（0）〜x（7） NOU）11至18通过电容器d0至d6。在每个NOU 11至18中，输入信号x（0）至x（7）被加和减。输入信号x（0）至x（7）预先乘以与连接到NOU 11至18的电容器d0至d6的电容成比例的系数。之后，离散余弦变换系数y（0）至y（7 ）被输出。通过使用一维离散余弦变换电路实现二维离散余弦变换电路。

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