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1. 发明授权

US08716130B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08716130B2
公开(公告)日：2014-05-06
申请号：US13643102
申请日：2011-04-04
申请人： Kippei Sugita , Kenji Matsuda , Hiroyuki Hashimoto , Muneo Harada
发明人： Kippei Sugita , Kenji Matsuda , Hiroyuki Hashimoto , Muneo Harada
IPC分类号： H01L21/44
CPC分类号： H01L21/283 , H01L21/0206 , H01L21/02063 , H01L21/31058 , H01L21/31138 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76898
摘要： The method includes forming a hole penetrating from one surface of a substrate to an electrode formed on the other surface of the substrate; forming an organic insulating film in the hole; removing at least a part of the organic insulating film formed in a bottom portion of the hole and not the organic insulating film formed on a side wall portion of the hole, to expose the electrode; cleaning an exposed surface of the electrode by using plasma of an inert gas; filling a conductive metal in the hole; removing at least a part of a surface of the organic insulating film by the reaction of oxygen plasma; and annealing the substrate in a dysoxidative atmosphere.
摘要翻译：该方法包括形成从衬底的一个表面穿透到形成在衬底的另一个表面上的电极的孔; 在孔中形成有机绝缘膜; 除去形成在孔的底部的有机绝缘膜的至少一部分，而不是形成在孔的侧壁部上的有机绝缘膜，以露出电极; 通过使用惰性气体的等离子体清洁电极的暴露表面; 在孔中填充导电金属; 通过氧等离子体的反应去除有机绝缘膜的至少一部分表面; 并在氧化性气氛中退火底物。

2. 发明授权

US08546185B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US08546185B2
公开(公告)日：2013-10-01
申请号：US13399482
申请日：2012-02-17
申请人： Ken Nakao , Muneo Harada , Itaru Iida , Eiji Yamaguchi
发明人： Ken Nakao , Muneo Harada , Itaru Iida , Eiji Yamaguchi
IPC分类号： H01L21/50
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/0401 , H01L2224/05551 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/11002 , H01L2224/11332 , H01L2224/11505 , H01L2224/13009 , H01L2224/13076 , H01L2224/13082 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13294 , H01L2224/13339 , H01L2224/8184 , H01L2224/81986 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2224/03 , H01L2224/11 , H01L2224/05552 , H01L2924/00
摘要： Provided is a method for manufacturing a semiconductor device which includes: providing a plurality of semiconductor substrates formed with through holes which penetrate between main surfaces of the substrates and are filled with porous conductors; stacking the plurality of semiconductor substrates while aligning the porous conductors filled in the through holes; introducing conductive ink containing particle-like conductors into the porous conductors of the plurality of stacked semiconductor substrates; and sintering the plurality of stacked semiconductor substrates.
摘要翻译：本发明提供一种半导体器件的制造方法，其特征在于，具备：多个半导体基板，形成有穿过所述基板的主面之间的通孔，并填充有多孔导体; 在对准填充在通孔中的多孔导体的同时堆叠多个半导体衬底; 将含有粒状导体的导电油墨引入到所述多个堆叠半导体衬底的多孔导体中; 并烧结多个堆叠的半导体衬底。

3. 发明授权

US07994443B2 Switch array 失效
标题翻译：开关阵列
公开(公告)号：US07994443B2
公开(公告)日：2011-08-09
申请号：US11886856
申请日：2006-03-20
申请人： Masato Hayashi , Masami Yakabe , Tetsuya Hasebe , Muneo Harada , Katsuya Okumura
发明人： Masato Hayashi , Masami Yakabe , Tetsuya Hasebe , Muneo Harada , Katsuya Okumura
IPC分类号： H01H1/00 , H01H9/00
CPC分类号： H01H1/0036 , B81B3/0054 , B81B2201/014 , B81B2203/053 , H01H1/24 , H01H37/46 , H01H67/22 , H01H2001/0042 , H01H2037/008
摘要： A first wiring layer 16 is disposed on an insulating film 14 on the lower surface of an upper substrate 15, while a second wiring layer 13three-dimensionally crossing the first wiring layer 16 is provided on the insulating film 12 on a lower substrate 11. A cantilever 17 has one end connected to the first wiring layer 16 and the other end opposed to the second wiring layer 13 with a space therebetween. A thermoplastic sheet 19 is arranged on the upper substrate 15 so as to cover the through-hole 18. The thermoplastic sheet 19 is pressed by a heated pin 20 against the cantilever 17 and deformed so as to maintain the connection between the cantilever 17and the second wiring layer 13, and therefore close the switch 10.
摘要翻译：第一布线层16设置在上基板15的下表面上的绝缘膜14上，而在下基板11上的绝缘膜12上设置与第一布线层16三维交叉的第二布线层13。悬臂17的一端与第一配线层16连接，另一端与第二配线层13相对置，而其间具有间隔。热塑片19布置在上基板15上以覆盖通孔18.热塑片19被加热的销20压靠在悬臂17上并变形，从而保持悬臂17和第二个之间的连接布线层13，因此闭合开关10。

4. 发明授权

US07742277B2 Dielectric film capacitor and method of manufacturing the same 有权
标题翻译：介电薄膜电容器及其制造方法
公开(公告)号：US07742277B2
公开(公告)日：2010-06-22
申请号：US11508204
申请日：2006-08-23
申请人： Tomotaka Shinoda , Kinji Yamada , Takahiro Kitano , Yoshiki Yamanishi , Muneo Harada , Tatsuzo Kawaguchi , Yoshihiro Hirota , Katsuya Okumura , Shuichi Kawano
发明人： Tomotaka Shinoda , Kinji Yamada , Takahiro Kitano , Yoshiki Yamanishi , Muneo Harada , Tatsuzo Kawaguchi , Yoshihiro Hirota , Katsuya Okumura , Shuichi Kawano
IPC分类号： H01G4/06 , H01G4/005
CPC分类号： H01L28/65 , H01L27/11507 , H01L28/55 , Y10T29/435
摘要： A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.
摘要翻译：电介质膜电容器包括具有开口并由包括铂的材料形成的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜和设置在电介质膜上的上电极。下部电极的平面面积为电介质膜的形成区域的面积的50％以上。电介质膜电容器包括由包括铂的材料形成的厚度为10至100nm的下电极，设置在下电极上并包括具有ABOx晶体结构的氧化物的电介质膜，以及设置在电介质上的上电极电影。

5. 发明申请

US20100032357A1 CHROMATOGRAPHY COLUMN AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：色谱柱及其制造方法
公开(公告)号：US20100032357A1
公开(公告)日：2010-02-11
申请号：US12377274
申请日：2007-08-14
申请人： Tomofumi Kiyomoto , Muneo Harada , Hiroyuki Moriyama , Katsuya Okumura
发明人： Tomofumi Kiyomoto , Muneo Harada , Hiroyuki Moriyama , Katsuya Okumura
IPC分类号： B01D15/08 , B44C1/22
CPC分类号： G01N30/6095 , G01N30/52 , G01N2030/525
摘要： A high separation efficiency column 10 for chromatography and a manufacturing method thereof are provided. The column 10 for chromatography includes a first substrate 11 having a plurality of pillars 22 formed on one surface thereof and a second substrate 12 bonded to the one surface of the first substrate 11 and constituting a flow path 13 together with the plurality of pillars 22 formed on the first substrate. At least a surface of each pillar is formed in a porous shape.
摘要翻译：提供了用于色谱法的高分离效率柱10及其制造方法。用于层析的柱10包括：第一基板11，其具有在其一个表面上形成的多个柱22;以及第二基板12，其与第一基板11的一个表面接合，并与形成的多个柱22一起构成流路13 在第一基板上。每个柱的至少一个表面形成为多孔形状。

6. 发明申请

US20060255182A1 Pattern forming apparatus and method of manufacturing pattern forming apparatus 审中-公开
标题翻译：图案形成装置和图案形成装置的制造方法
公开(公告)号：US20060255182A1
公开(公告)日：2006-11-16
申请号：US11411983
申请日：2006-04-27
申请人： Katsuya Okumura , Manabu Yabe , Yasuyuki Koyagi , Muneo Harada , Tomofumi Kiyomoto
发明人： Katsuya Okumura , Manabu Yabe , Yasuyuki Koyagi , Muneo Harada , Tomofumi Kiyomoto
IPC分类号： B05B1/26 , B05B1/34
CPC分类号： B41J2/1609 , B05C5/007 , B05C5/0212 , B05C5/027 , B41J2/1628 , B41J2/1631 , H01J9/242
摘要： Using a silicon single crystal with (100) plane orientation as a base material, a pectinate portion having a slope portion and a patterning material guiding groove is formed through photolithography process. A liquid reservoir for keeping a patterning material common to tooth portions of the pectinate portion is formed in the same step as a step for forming the guiding grooves. In forming slope portion, anisotropic wet etching allows easy and accurate formation of a slope portion with (111) plane orientation to (100) plane orientation, by taking advantage of differences in speed due to the plane orientations. In addition, by forming a groove portion using anisotropic dry etching, the patterning material guiding groove having a perpendicular sidewall reaching the slope portion may be formed at high accuracy. A pattern forming apparatus with high accuracy and low cost is provided.
摘要翻译：使用具有（100）面取向的硅单晶作为基材，通过光刻工艺形成具有倾斜部分和图案形成材料引导槽的果胶部分。在与用于形成导向槽的步骤相同的步骤中形成用于保持图形材料的共同于图形部分的牙齿部分的图案材料的液体储存器。在形成斜坡部分时，通过利用由于平面取向的速度差异，各向异性湿蚀刻允许容易且准确地形成具有（111）面取向到（100）面取向的斜面部分。此外，通过使用各向异性干蚀刻形成槽部，可以高精度地形成具有到达斜面部的垂直侧壁的图案形成材料导向槽。提供了一种高精度，低成本的图案形成装置。

7. 发明授权

US06331780B1 Static capacitance-to-voltage converter and converting method 有权
标题翻译：静态电容电压转换器及其转换方法
公开(公告)号：US06331780B1
公开(公告)日：2001-12-18
申请号：US09381780
申请日：1999-09-23
申请人： Tatsuo Hiroshima , Koichi Nakano , Muneo Harada , Toshiyuki Matsumoto , Yoshihiro Hirota
发明人： Tatsuo Hiroshima , Koichi Nakano , Muneo Harada , Toshiyuki Matsumoto , Yoshihiro Hirota
IPC分类号： G01R2726
CPC分类号： G01R27/2605
摘要： A static capacitance-to-voltage converter is capable of converting a static capacitance into a voltage without suffering from a stray capacitance formed between a signal and a shielding line or a stray capacitance formed between an exposed portion of the signal line and its surroundings. The static capacitance-to-voltage converter is formed of an operational amplifier placed in an imaginary short-circuit state between an inverting input and a non-inverting input thereof; a signal line having one end connected to the inverting input and the other end capable of being connected to a static capacitance; a shielding line surrounding the signal line and connected to the non-inverting input; an alternating current signal generator for applying the non-inverting input with an alternating current signal; and zero adjusters for adjusting the output of the static capacitance-to-voltage converter to minimum when no static capacitance is connected to the signal line.
摘要翻译：静态电容 - 电压转换器能够将静态电容转换成电压，而不会在信号线与屏蔽线之间形成的寄生电容或信号线的暴露部分与其周围环境之间形成的杂散电容。静态电容 - 电压转换器由在反相输入端和非反相输入端之间以假想短路状态放置的运算放大器形成; 信号线，其一端连接到反相输入，另一端能够连接到静态电容; 围绕信号线并连接到非反相输入的屏蔽线; 交流信号发生器，用于以交流信号施加所述非反相输入; 以及用于在静态电容连接到信号线时将静态电容 - 电压转换器的输出调整到最小的零点调整器。

8. 发明授权

US6079274A Vibration wave detecting method and vibration wave detector 失效
标题翻译：振动波检测方法和振动波检测器
公开(公告)号：US6079274A
公开(公告)日：2000-06-27
申请号：US316586
申请日：1999-05-21
申请人： Shigeru Ando , Muneo Harada
发明人： Shigeru Ando , Muneo Harada
IPC分类号： G01H1/06 , G01H11/08 , G01H11/00
CPC分类号： G01H11/08 , G01H1/06
摘要： A vibration wave detector in which: a plurality of resonator beams, each having a different length and being allowed to resonate at a specific frequency, are provided; a piezoresistor is installed in each resonator beam; and the piezoresistors are parallel-connected so that vibration is converted to an electric signal by the piezoresistors so as to output the sum of vibration waveforms at the respective resonator beams. It is possible to control a gain of a specific frequency band by changing a voltage to be applied to the parallel circuit or changing the resistance value of each piezoresistor.
摘要翻译：一种振动波检测器，其特征在于：提供多个具有不同长度并被允许以特定频率谐振的谐振器束; 每个谐振器梁中安装一个压敏电阻; 并且压电电阻器并联连接，从而通过压阻电阻器将振动转换成电信号，以输出各个谐振器波束的振动波形之和。可以通过改变施加到并联电路的电压或改变每个压敏电阻器的电阻值来控制特定频带的增益。

9. 发明申请

US20150214088A1 PICKUP METHOD AND PICKUP DEVICE 审中-公开
标题翻译：撷取方法和撷取装置
公开(公告)号：US20150214088A1
公开(公告)日：2015-07-30
申请号：US13819033
申请日：2011-06-30
申请人： Ken Nakao , Michikazu Nakamura , Itaru Iida , Muneo Harada
发明人： Ken Nakao , Michikazu Nakamura , Itaru Iida , Muneo Harada
IPC分类号： H01L21/683 , B32B43/00 , H01L21/67 , B25J15/06
CPC分类号： H01L21/6835 , B25J15/0616 , B32B43/006 , H01L21/67011 , H01L21/67132 , H01L21/6836 , H01L21/6838 , H01L2221/68327 , Y10T156/1132 , Y10T156/1933
摘要： Disclosed is a pickup method in which a first suction unit is caused to approach and come into contact with a chip adhered to an adhesive sheet, and a second suction unit which is formed with a concavity on a contact surface configured to come into contact with the adhesive sheet is caused to approach and come into contact with the adhesive sheet in such a manner as to be opposite to the first suction unit. The adhesive sheet is sucked by the second suction unit that is in contact with the adhesive sheet, and a fluid is injected between the adhesive sheet and the chip by an injection unit. As a result, the adhesive sheet is detached from a portion of the chip opposite to the concavity, and in the state where the chip is being sucked by the first suction unit, the first suction unit is caused to be spaced away from the adhesive sheet that is being sucked by the second suction unit. In this manner, the chip is detached and picked up from the adhesive sheet.
摘要翻译：公开了一种拾取方法，其中使第一吸引单元接近并与粘附到粘合片上的芯片接触;以及第二抽吸单元，其形成在接触表面上的与凹部接触的接触表面上的凹部使粘合片以与第一抽吸单元相对的方式接近并与粘合片接触。通过与粘合片接触的第二抽吸单元吸附粘合片，并且通过注射单元将流体注入粘合片和芯片之间。结果，粘合片与芯片的与凹部相反的部分分离，并且在芯片被第一吸引单元吸附的状态下，使第一吸引单元与粘合片隔开其被第二抽吸单元吸入。以这种方式，将芯片从粘合片上分离并拾取。

10. 发明授权

US08470720B2 Film forming apparatus and film forming method 有权
标题翻译：成膜装置及成膜方法
公开(公告)号：US08470720B2
公开(公告)日：2013-06-25
申请号：US12934165
申请日：2009-03-16
申请人： Ken Nakao , Muneo Harada
发明人： Ken Nakao , Muneo Harada
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： C23C14/12 , B05D1/60 , B05D3/0473 , B05D3/0493 , C23C14/243 , H01L21/02126 , H01L21/02312 , H01L21/312
摘要： A wall surface of a film forming container is heated to or above a vaporization temperature of a material monomer, which is used to form an organic film, by using an external heater formed along the wall surface of the film forming container, substrates are heated to a thermal polymerization reaction temperature by using an internal heater that is disposed apart from the external heater and near a substrate-supporting container in which the substrates are received, and the organic film is formed through thermal polymerization occurring on the substrates by supplying the material monomer into the film forming container.
摘要翻译：通过使用沿着成膜容器的壁面形成的外部加热器将成膜容器的壁面加热至或高于用于形成有机膜的材料单体的蒸发温度，将基板加热至通过使用与外部加热器隔离的内部加热器和接收基板的基板支撑容器附近的内部加热器，形成热聚合反应温度，并且通过在基板上进行热聚合而形成有机膜，所述热聚合通过供给材料单体进入成膜容器。

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