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    • 71. 发明授权
    • System for use of packet statistics in de-jitter delay adaption in a packet network
    • 在分组网络中去抖动延迟适应中使用分组统计的系统
    • US06693921B1
    • 2004-02-17
    • US09452088
    • 1999-11-30
    • Michael C. Whitfield
    • Michael C. Whitfield
    • H04J306
    • H04L47/29H04J3/0632H04L47/10H04L47/283H04L47/34
    • A system which compensates for jitter in the transfer of voice data over packet data networks. A predetermined quality of service factor is used to determine the jitter delay for received voice packets in order to optimize the number of voice packets received. The invention uses packet sequence information in the voice packet protocol to determine which voice packets are missing and which voice packets are late within a predetermined statistically significant interval. The jitter delay is decreased when the number of missing packets is significantly less than that specified by the quality of service factor. In most cases, the jitter delay is increased when the number of missing packets is greater than that specified by the quality of service factor. The jitter delay is not increased past a certain value when no late packets are observed during the predetermined interval.
    • 一种补偿通过分组数据网络传输语音数据的抖动的系统。 使用预定的服务质量因子来确定接收的语音分组的抖动延迟,以便优化所接收的语音分组的数量。 本发明使用语音分组协议中的分组序列信息来确定哪个语音分组丢失,哪个语音分组在预定的统计学显着的间隔内是迟到的。 当丢失数据包的数量明显小于由服务质量因素指定的数量时,抖动延迟会减少。 在大多数情况下,当丢失数据包的数量大于由服务质量因素指定的数量时,抖动延迟会增加。 当在预定间隔期间没有观察到延迟的分组时,抖动延迟不会增加超过特定值。
    • 73. 发明授权
    • Wireless communication system and control method therefor
    • 无线通信系统及其控制方法
    • US06671270B2
    • 2003-12-30
    • US08816968
    • 1997-03-13
    • Hidetada Nago
    • Hidetada Nago
    • H04J306
    • H04W56/00H04B7/2681H04W74/04
    • A wireless communication apparatus which performs communication control on wireless communication apparatuses in a predetermined cell of a predetermined range. When information on synchronization transmitted from a wireless communication apparatus in the adjacent cell has been received, frame/communication synchronization is established with respect to the adjacent cell, and communication control is performed in the predetermined cell, based on the information. Upon transmitting information for synchronization to the wireless communication apparatuses in the cell, the information is sent in a time slot, different from a time slot used for receiving the synchronizing information from the wireless communication apparatus in the adjacent cell, in the same communication frame.
    • 一种在预定范围的预定单元中对无线通信装置进行通信控制的无线通信装置。 当接收到相邻小区中的无线通信装置发送的同步信息时,基于相邻小区建立帧/通信同步,并根据该信息在预定小区中进行通信控制。 在向小区中的无线通信装置发送用于同步的信息时,在相同通信帧中,在与相邻小区中的无线通信装置接收同步信息所用的时隙不同的时隙中发送该信息。
    • 74. 发明授权
    • Synchronizing source-synchronous links in a switching device
    • 在交换设备中同步源同步链路
    • US06636518B1
    • 2003-10-21
    • US09129261
    • 1998-08-04
    • Bjorn O. Liencres
    • Bjorn O. Liencres
    • H04J306
    • H04L49/9021H04J3/0632H04L7/041H04L7/10H04L12/56H04L12/5601H04L29/06H04L45/00H04L47/6225H04L49/108H04L49/203H04L49/3081H04L49/608H04L49/90H04L49/901H04L49/9047H04L69/22H04L2012/5652H04L2012/5674H04L2012/5679H04Q11/0478
    • A method and apparatus for synchronizing components operating isochronously that are coupled by independent links. The apparatus includes a synchronization circuit having a first and second buffer, each including an input port coupled to an external link, an output port, a read pointer and a write pointer. The read pointer indicates a next location in a respective buffer to be read in transferring data out on the output port. The write pointer indicates a next location in the respective buffer to be written when receiving data on the input port and is configured to automatically increment upon receipt of a first data bit on a respective external link. A trigger circuit is coupled to each link for receiving external trigger signals. Each external trigger signal is included along with data transmitted on the link and indicates when data is present on a respective link. A counter is coupled to the trigger circuit. The counter includes a trigger input and a predefined delay period. After receipt of a first of the external trigger signals on the trigger input, the counter is operable to output a read enable signal to each of the read pointers after the delay period has expired.
    • 一种用于使通过独立链路耦合的等时运行的组件同步的方法和装置。 该装置包括具有第一和第二缓冲器的同步电路,每个缓冲器包括耦合到外部链路的输入端口,输出端口,读取指针和写入指针。 读指针指示在输出端口上传送数据时要读取的相应缓冲器中的下一个位置。 写指针指示在接收输入端口上的数据时要写入的相应缓冲器中的下一位置,并且被配置为在接收到相应外部链路上的第一数据位时自动递增。 触发电路耦合到每个链路以用于接收外部触发信号。 每个外部触发信号与在链路上发送的数据一起被包括,并且指示何时在相应的链路上存在数据。 计数器耦合到触发电路。 计数器包括触发输入和预定义的延迟时间。 在触发输入上接收到第一外部触发信号之后,计数器可操作以在延迟时间期满之后将读使能信号输出到每个读指针。
    • 75. 发明授权
    • Method of synchronizing a reference clock of a ground station and a clock of a remote system
    • 同步地面站的参考时钟和远程系统的时钟的方法
    • US06633590B1
    • 2003-10-14
    • US09521851
    • 2000-03-09
    • Giovanni GarofaloGiovanni Busca
    • Giovanni GarofaloGiovanni Busca
    • H04J306
    • H04B7/2125
    • The invention relates to a method of synchronizing a reference clock of a first ground station and a local clock of a remote system, in particular a satellite. It includes: a) acquisition in a first loop of synchronization between reference bursts received by the remote system and generated bursts synchronized with the local clock, b) detection of the recognition word of the reference bursts received by the first remote system and generation of a time window containing N pulses of the reference clock, c) acquisition of the average phase of said pulses and comparison with the phase of the local clock, and d) in a second loop, synchronization of the phase of the local clock with said average phase. The method can be reiterated to synchronize a second ground station with the first one via the remote system.
    • 本发明涉及一种使第一地面站的参考时钟和远程系统的本地时钟(特别是卫星)同步的方法。 它包括:a)在由远程系统接收的参考突发之间的第一个同步循环中获取并产生与本地时钟同步的脉冲串b)检测由本地时钟接收的参考突发的识别字 第一个远程系统和生成包含参考时钟的N个脉冲的时间窗口,c)获取所述脉冲的平均相位并与本地时钟的相位进行比较,并且在 第二个循环,本地时钟的相位与所述平均相位的同步。可以重复该方法,以通过远程系统将第二个地面站与第一个地面站同步。
    • 76. 发明授权
    • Systems and methods for communicating messages among cascaded devices by bit shifting
    • 用于通过位移动在级联设备之间传送消息的系统和方法
    • US06628676B1
    • 2003-09-30
    • US09337448
    • 1999-06-21
    • Ossi I. GrohnAnthony S. Fugaro
    • Ossi I. GrohnAnthony S. Fugaro
    • H04J306
    • H04B7/2656H04W88/085
    • Messages are communicated among a plurality of devices that are serially connected, such that a preceding device is connected to a succeeding device, by receiving a message from a preceding device, bit shifting the message that was received from the preceding device and transmitting the bit shifted message that was received from the preceding device to a succeeding device. When a message is received from a succeeding device, it also is bit shifted and the bit shifted message that was received from the succeeding device is transmitted to the preceding device. Preferably, messages that are received from the preceding device are shifted in a first direction such as left by a predetermined number of bits and messages that are received from the succeeding device are shifted in a second direction that is opposite the first direction such as right by the predetermined number of bits. Preferably, the predetermined number of bits corresponds to at least one TDMA slot. Prior to shifting the message that was received from the preceding device left by the predetermined number of bits, the predetermined number of leftmost bits is extracted from the message that was received from the preceding device. Moreover, after shifting the message that was received from the succeeding device right by the predetermined number of bits, the predetermined number of bits is inserted into the leftmost part of the message that was received from the succeeding device. Accordingly, each of the cascaded devices preferably extracts a downlink message from at least the first TDMA slot and then shifts the downlink message to the left by at least one slot. Similarly, each of the cascaded devices shifts an uplink TDMA message to the right by at least one slot and inserts its message into at least the first slot.
    • 在串行连接的多个设备之间传送消息,使得先前的设备通过从前一设备接收到消息,对从先前设备接收到的消息进行位移位并发送位移 从上一个设备接收的消息到后续设备。 当从后续设备接收到消息时,它也被位移,并且从后续设备接收到的位移消息被发送到前一个设备。 优选地,从先前设备接收到的消息在诸如左边预定位数的第一方向上移位,并且从后续设备接收到的消息在与第一方向相反的第二方向上偏移,例如右 预定位数。 优选地,预定数量的比特对应于至少一个TDMA时隙。 在将从先前设备接收到的消息移动了预定位数之前,从从先前设备接收到的消息中提取预定数量的最左位。 此外,在将从后续设备接收到的消息右移到预定位数之后,将预定数量的比特插入到从后续设备接收的消息的最左部分中。 因此,每个级联设备优选地从至少第一TDMA时隙提取下行链路消息,然后将下行链路消息向左移动至少一个时隙。 类似地,每个级联设备将上行链路TDMA消息向右移动至少一个时隙,并将其消息插入至少第一时隙。
    • 78. 发明授权
    • OC-3 delivery unit; timing architecture
    • OC-3送货单位 定时架构
    • US06608844B1
    • 2003-08-19
    • US09391316
    • 1999-09-07
    • Valentine TeodorescuLong Van Vo
    • Valentine TeodorescuLong Van Vo
    • H04J306
    • H04J3/0685H04J2203/0008H04J2203/0021H04J2203/0025H04J2203/0089
    • A timing architecture for a delivery unit that interfaces telecommunications media to a switching matrix. The delivery unit is functionally partitioned into a number of application modules. Transport between the modules is handled by a bus control module, with ingress buses from the application modules to the bus control module and egress buses from the bus control module to the application module. The bus control module also distributes system timing signals to each application module on these buses. The application modules each have a common bus interface that derives common local timing signals. They also each have a common local timebase that derives additional local timing signals. The bus interface is also used to deliver synchronization signals back to the bus control module.
    • 用于将电信媒体与交换矩阵相连接的传送单元的定时架构。 交付单元在功能上划分为多个应用模块。 模块之间的传输由总线控制模块处理,其中从应用模块到总线控制模块的入口总线和从总线控制模块到应用模块的出口总线。 总线控制模块还将系统定时信号分配到这些总线上的每个应用模块。 每个应用模块都有一个公共总线接口,可以导出公共的本地定时信号。 它们每个都有一个通用的本地时基,可以获得额外的本地时序信号。 总线接口也用于将同步信号传送回总线控制模块。
    • 79. 发明授权
    • Method and apparatus for establishing frame synchronization
    • 用于建立帧同步的方法和装置
    • US06603777B1
    • 2003-08-05
    • US09310103
    • 1999-05-12
    • Atsuhiro Kubota
    • Atsuhiro Kubota
    • H04J306
    • H04J3/0608
    • The present invention provides a frame synchronous circuit wherein the number of devices handling a high-speed digital signal is limited to the minimum without deteriorating frame pull-in time and an erroneous synchronization rate. For the sake of it, synchronous word decision devices decide frame synchronization from four lines of low-speed digital signals into which the high-speed digital signal is converted by a serial-parallel converter. An OR circuit synthesizes respective outputs of the synchronous word decision devices, and an aperture circuit applies an aperture to the output synthesized. A selection circuit fetches only one output corresponding to the change of the apparent synchronous word after establishment of synchronization. A frame counter circuit estimates a predetermined position of the next frame at the time of applying a narrow aperture. A leading-edge positioning/column change circuit performs leading-edge positioning and column change of data to the output of the selection circuit.
    • 本发明提供了一种帧同步电路,其中处理高速数字信号的设备的数量被限制到最小,而不会降低帧引入时间和错误的同步速率。 为此,同步字决策装置决定了由串行并行转换器转换高速数字信号的四行低速数字信号的帧同步。 OR电路合成同步字决定装置的各个输出,并且孔径电路对合成的输出施加孔径。 选择电路仅在建立同步之后仅获取对应于表观同步字的变化的一个输出。 帧计数器电路估计在施加窄光圈时下一帧的预定位置。 前沿定位/列更改电路执行前沿定位和数据列更改到选择电路的输出。